公开(公告)号：US5441900A

公开(公告)日：1995-08-15

申请号：US308698

申请日：1994-09-19

Applicant: Constantin Bulucea ,  Esin Dermirlioglu ,  Sheldon Aronowitz

Inventor： Constantin Bulucea ,  Esin Dermirlioglu ,  Sheldon Aronowitz

IPC: H01L27/092 ,  H01L21/265

CPC classification number: H01L27/0921 ,  Y10S148/023 ,  Y10S438/904 ,  Y10S438/917

Abstract: A unique approach to suppressing latchup in CMOS structures is described. Atomic species that exhibit midgap levels in silicon and satisfy the criteria for localized action and electrical compatibility can be implanted to suppress the parasitic bipolar behavior which causes latchup. Reduction of minority carrier lifetime can be achieved in critical parasitic bipolar regions that, by CMOS construction are outside the regions of active MOS devices. One way to accomplish this goal is to use the source/drain masks to locally implant the minority carrier lifetime reducer (MCLR) before the source/drain dopants are implanted. This permits the MCLR to be introduced at different depths or even to be different species, of the n and p-channel transistors. Another way to accomplish this goal requires that a blanket MCLR implant be done very early in the process, before isolation oxidation, gate oxidation or active threshold implants are done.

Abstract translation: 描述了抑制CMOS结构中的闭锁的独特方法。 可以植入在硅中显示中间水平并满足局部作用和电相容性标准的原子物质，以抑制引起闭锁的寄生双极性行为。 通过CMOS结构在有源MOS器件区域之外的临界寄生双极区域可以实现少数载流子寿命的降低。 实现这一目标的一个方法是在源极/漏极掺杂剂被植入之前，使用源极/漏极掩模来局部注入少数载流子寿命衰减器（MCLR）。 这允许MCLR在n沟道晶体管和p沟道晶体管的不同深度或者甚至不同的物种中被引入。 实现这一目标的另一种方法是要求在隔离氧化，栅极氧化或活性阈值植入完成之前，在该过程中非常早地完成覆盖MCLR植入物。

公开(公告)号：US08610207B2

公开(公告)日：2013-12-17

申请号：US13298283

申请日：2011-11-16

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L21/8238

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated-gate field-effect transistor (220U) utilizes an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (262 and 264), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (136U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (262M or 264M) and a more lightly doped lateral extension (262E or 264E). Alternatively or additionally, a more heavily doped pocket portion (280) of the body material extends along one of the source/drain zones.

Abstract translation: 绝缘栅场效应晶体管（220U）利用空阱区实现高性能。 身体掺杂物的浓度在上半导体表面下方比在一对源/漏区（262和264）之一的深度不超过10倍的地下位置处达到最大值，减小至少一个因子 10沿着沿着选择的垂直线（136U）通过该源极/漏极区域移动到上半导体表面的地下位置移动，并且具有从沿着垂直线的地下位置移动到基本单调和基本上无穷地减小的对数， 源/漏区。 每个源/漏区具有主要部分（262M或264M）和更轻掺杂的横向延伸（262E或264E）。 替代地或另外地，主体材料的更重掺杂的凹穴部分（280）沿着源极/漏极区域中的一个延伸。

公开(公告)号：US08502273B2

公开(公告)日：2013-08-06

申请号：US12908458

申请日：2010-10-20

Applicant: Sandeep Bahl ,  Constantin Bulucea

Inventor： Sandeep Bahl ,  Constantin Bulucea

IPC: H01L29/778 ,  H01L21/338

CPC classification number: H01L29/7787 ,  H01L29/2003 ,  H01L29/66462

Abstract: The buffer breakdown of a group III-N HEMT on a p-type Si substrate is significantly increased by forming an n-well in the p-type Si substrate to lie directly below the metal drain region of the group III-N HEMT. The n-well forms a p-n junction which becomes reverse biased during breakdown, thereby increasing the buffer breakdown by the reverse-biased breakdown voltage of the p-n junction and allowing the substrate to be grounded. The buffer layer of a group III-N HEMT can also be implanted with n-type and p-type dopants which are aligned with the p-n junction to minimize any leakage currents at the junction between the substrate and the buffer layer.

Abstract translation: 通过在p型Si衬底中形成n阱以直接位于III-NHEMT族金属漏极区的下方，在p型Si衬底上的III-N HEMT组的缓冲击穿显着增加。 n阱形成在击穿期间变得反向偏置的p-n结，从而通过p-n结的反向偏置击穿电压增加缓冲器击穿，并允许衬底接地。 III-N型HEMT的缓冲层也可以注入与p-n结对准的n型和p型掺杂剂，以最小化衬底和缓冲层之间的接合处的任何漏电流。

公开(公告)号：US20130126983A1

公开(公告)日：2013-05-23

申请号：US13298283

申请日：2011-11-16

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L29/78

CPC classification number: H01L21/823892 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1045 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: An insulated-gate field-effect transistor (220U) utilizes an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (262 and 264), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (136U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (262M or 264M) and a more lightly doped lateral extension (262E or 264E). Alternatively or additionally, a more heavily doped pocket portion (280) of the body material extends along one of the source/drain zones.

Abstract translation: 绝缘栅场效应晶体管（220U）利用空阱区实现高性能。 身体掺杂物的浓度在上半导体表面下方比在一对源/漏区（262和264）之一的深度不超过10倍的地下位置处达到最大值，减小至少一个因子 10沿着沿着选择的垂直线（136U）通过该源极/漏极区域移动到上半导体表面的地下位置移动，并且具有从沿着垂直线的地下位置移动到基本单调和基本上无穷地减小的对数， 源/漏区。 每个源/漏区具有主要部分（262M或264M）和更轻掺杂的横向延伸（262E或264E）。 替代地或另外地，主体材料的更重掺杂的凹穴部分（280）沿着源极/漏极区域中的一个延伸。

公开(公告)号：US08304835B2

公开(公告)日：2012-11-06

申请号：US12382973

申请日：2009-03-27

Applicant: Constantin Bulucea ,  Sandeep R. Bahl ,  William D. French ,  Jeng-Jiun Yang ,  Donald M. Archer ,  D. Courtney Parker ,  Prasad Chaparala

Inventor： Constantin Bulucea ,  Sandeep R. Bahl ,  William D. French ,  Jeng-Jiun Yang ,  Donald M. Archer ,  D. Courtney Parker ,  Prasad Chaparala

IPC: H01L29/36

CPC classification number: H01L27/088 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.

Abstract translation: 作为半导体制造平台的核心的半导体结构具有由电子元件特别是绝缘栅场效应晶体管（IGFET）不同地使用的空阱区域和填充阱区域的组合，以实现期望的电子 特点 相当少量的半导体阱掺杂剂靠近空穴的顶部。 相当数量的半导体阱掺杂剂靠近填充井的顶部。 一些IGFET（100,102,112,114,124和126）利用空井（180,182,192,194,204和206）实现期望的晶体管特性。 其它IGFET（108,110,116,118,120和122）利用填充的孔（188,190,196,198,200和202）实现期望的晶体管特性。 空孔和填充孔的组合使得半导体制造平台能够提供各种各样的高性能IGFET，电路设计者可以从其中选择特定的IGFET用于各种模拟和数字应用，包括混合信号应用。

公开(公告)号：US08304308B2

公开(公告)日：2012-11-06

申请号：US13198601

申请日：2011-08-04

Applicant: Jeng-Jiun Yang ,  Constantin Bulucea

Inventor： Jeng-Jiun Yang ,  Constantin Bulucea

IPC: H01L27/06

CPC classification number: H01L27/0623 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0826

Abstract: A semiconductor structure contains a bipolar transistor (101) and a spacing structure (265-1 or 265-2). The transistor has an emitter (241), a base (243), and a collector (245). The base is formed with an intrinsic base portion (243I), a base link portion (243L), and a base contact portion (245C). The intrinsic base portion is situated below the emitter and above material of the collector. The base link portion extends between the intrinsic base portion and the base contact portions. The spacing structure includes an isolating dielectric layer (267-1 or 267-2) and a spacing component. The dielectric layer extends along the upper semiconductor surface. The spacing component includes a lateral spacing portion (269-1 or 269-2) of largely non-monocrystalline semiconductor material, preferably polycrystalline semiconductor material, situated on the dielectric layer above the base link portion. Opposite first and second upper edges of the lateral spacing portion (275-1 and 277-1) laterally conform to opposite first and second lower edges (297-1 and 299-1) of the base link portion so as to determine, and thereby control, its length.

Abstract translation: 半导体结构包含双极晶体管（101）和间隔结构（265-1或265-2）。 晶体管具有发射极（241），基极（243）和集电极（245）。 基部形成有本征基部（243I），基部连接部（243L）和基部接触部（245C）。 本征基部位于发射极之下和集电极材料之上。 基部连接部在本征基部与基部接触部之间延伸。 间隔结构包括隔离电介质层（267-1或267-2）和间隔部件。 电介质层沿着上半导体表面延伸。 间隔部件包括位于基部连接部分上方的电介质层上的大部分非单晶半导体材料（优选多晶半导体材料）的侧向间隔部分（269-1或269-2）。 横向间隔部分（275-1和277-1）的相对的第一和第二上边缘横向地与基部连杆部分的相对的第一和第二下边缘（297-1和299-1）相一致，以便确定，从而 控制，其长度。

公开(公告)号：US20120181626A1

公开(公告)日：2012-07-19

申请号：US13298284

申请日：2011-11-16

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/1203

Abstract: An insulated-gate field-effect transistor (220U) is provided with an empty-well region for achieving high performance. The concentration of the body dopant reaches a maximum at a subsurface location no more than 10 times deeper below the upper semiconductor surface than the depth of one of a pair of source/drain zones (262 and 264), decreases by at least a factor of 10 in moving from the subsurface location along a selected vertical line (136U) through that source/drain zone to the upper semiconductor surface, and has a logarithm that decreases substantially monotonically and substantially inflectionlessly in moving from the subsurface location along the vertical line to that source/drain zone. Each source/drain zone has a main portion (262M or 264M) and a more lightly doped lateral extension (262E or 264E). Alternatively or additionally, a more heavily doped pocket portion (280) of the body material extends along one of the source/drain zones.

Abstract translation: 绝缘栅场效应晶体管（220U）具有用于实现高性能的空井区域。 身体掺杂物的浓度在上半导体表面下方比在一对源/漏区（262和264）之一的深度不超过10倍的地下位置处达到最大值，减小至少一个因子 10沿着沿着选择的垂直线（136U）通过该源极/漏极区域移动到上半导体表面的地下位置移动，并且具有从沿着垂直线的地下位置移动到基本单调和基本上无穷地基本上单调减小的对数， 源/漏区。 每个源/漏区具有主要部分（262M或264M）和更轻掺杂的横向延伸（262E或264E）。 替代地或另外地，主体材料的更重掺杂的凹穴部分（280）沿着源极/漏极区域中的一个延伸。

公开(公告)号：US20100244143A1

公开(公告)日：2010-09-30

申请号：US12382966

申请日：2009-03-27

Applicant: Jeng-Jiun Yang ,  Constantin Bulucea

Inventor： Jeng-Jiun Yang ,  Constantin Bulucea

IPC: H01L27/06 ,  H01L27/082 ,  H01L21/8228 ,  H01L21/8249

CPC classification number: H01L27/0623 ,  H01L21/82285 ,  H01L21/8249 ,  H01L27/0826

Abstract: A semiconductor structure contains a bipolar transistor (101) and a spacing structure (265-1 or 265-2). The transistor has an emitter (241), a base (243), and a collector (245). The base is formed with an intrinsic base portion (243I), a base link portion (243L), and a base contact portion (245C). The intrinsic base portion is situated below the emitter and above material of the collector. The base link portion extends between the intrinsic base portion and the base contact portions. The spacing structure includes an isolating dielectric layer (267-1 or 267-2) and a spacing component. The dielectric layer extends along the upper semiconductor surface. The spacing component includes a lateral spacing portion (269-1 or 269-2) of largely non-monocrystalline semiconductor material, preferably polycrystalline semiconductor material, situated on the dielectric layer above the base link portion. Opposite first and second upper edges of the lateral spacing portion (275-1 and 277-1) laterally conform to opposite first and second lower edges (297-1 and 299-1) of the base link portion so as to determine, and thereby control, its length.

Abstract translation: 半导体结构包含双极晶体管（101）和间隔结构（265-1或265-2）。 晶体管具有发射极（241），基极（243）和集电极（245）。 基部形成有本征基部（243I），基部连接部（243L）和基部接触部（245C）。 本征基部位于发射极之下和集电极材料之上。 基部连接部在本征基部与基部接触部之间延伸。 间隔结构包括隔离电介质层（267-1或267-2）和间隔部件。 电介质层沿着上半导体表面延伸。 间隔部件包括位于基部连接部分上方的电介质层上的大部分非单晶半导体材料（优选多晶半导体材料）的侧向间隔部分（269-1或269-2）。 横向间隔部分（275-1和277-1）的相对的第一和第二上边缘横向地与基部连杆部分的相对的第一和第二下边缘（297-1和299-1）相一致，以便确定，从而 控制，其长度。

公开(公告)号：US20100244128A1

公开(公告)日：2010-09-30

申请号：US12382973

申请日：2009-03-27

Applicant: Constantin Bulucea ,  Sandeep R. Bahl ,  William D. French ,  Jeng-Jiun Yang ,  Donald M. Archer ,  D. Courtney Parker ,  Prasad Chaparala

Inventor： Constantin Bulucea ,  Sandeep R. Bahl ,  William D. French ,  Jeng-Jiun Yang ,  Donald M. Archer ,  D. Courtney Parker ,  Prasad Chaparala

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L27/088 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

Abstract: A semiconductor structure, which serves as the core of a semiconductor fabrication platform, has a combination of empty-well regions and filled-well regions variously used by electronic elements, particularly insulated-gate field-effect transistors (“IGFETs”), to achieve desired electronic characteristics. A relatively small amount of semiconductor well dopant is near the top of an empty well. A considerable amount of semiconductor well dopant is near the top of a filled well. Some IGFETs (100, 102, 112, 114, 124, and 126) utilize empty wells (180, 182, 192, 194, 204, and 206) in achieving desired transistor characteristics. Other IGFETs (108, 110, 116, 118, 120, and 122) utilize filled wells (188, 190, 196, 198, 200, and 202) in achieving desired transistor characteristics. The combination of empty and filled wells enables the semiconductor fabrication platform to provide a wide variety of high-performance IGFETs from which circuit designers can select particular IGFETs for various analog and digital applications, including mixed-signal applications.

Abstract translation: 作为半导体制造平台的核心的半导体结构具有由电子元件特别是绝缘栅场效应晶体管（“IGFET”）不同地使用的空阱区域和填充阱区域的组合，以实现 所需的电子特性。 相当少量的半导体阱掺杂剂靠近空穴的顶部。 相当数量的半导体阱掺杂剂靠近填充井的顶部。 一些IGFET（100,102,112,114,124和126）利用空井（180,182,192,194,204和206）实现期望的晶体管特性。 其它IGFET（108,110,116,118,120和122）利用填充的孔（188,190,196,198,200和202）实现期望的晶体管特性。 空孔和填充孔的组合使得半导体制造平台能够提供各种各样的高性能IGFET，电路设计者可以从其中选择特定的IGFET用于各种模拟和数字应用，包括混合信号应用。

公开(公告)号：US07642574B2

公开(公告)日：2010-01-05

申请号：US11981481

申请日：2007-10-31

Applicant: Constantin Bulucea

Inventor： Constantin Bulucea

IPC: H01L27/088

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/1203 ,  H01L27/1207

Abstract: An insulated-gate field-effect transistor (100, 100V, 140, 150, 150V, 160, 170, 170V, 180, 180V, 190, 210, 210W, 220, 220U, 220V, 220W, 380, or 480) has a hypoabrupt vertical dopant profile below one (104 or 264) of its source/drain zones for reducing the parasitic capacitance along the pn junction between that source/drain zone and adjoining body material (108 or 268). In particular, the concentration of semiconductor dopant which defines the conductivity type of the body material increases by at least a factor of 10 in moving from that source/drain zone down to an underlying body-material location no more than 10 times deeper below the upper semiconductor surface than that source/drain zone. The body material preferably includes a more heavily doped pocket portion (120 or 280) situated along the other source/drain zone (102 or 262). The combination of the hypoabrupt vertical dopant profile below the first-mentioned source/drain zone, normally serving as the drain, and the pocket portion along the second-mentioned source/drain zone, normally serving as the source, enables the resultant asymmetric transistor to be especially suitable for high-speed analog applications.

Abstract translation: 绝缘栅场效应晶体管（100,100V，140,150,150V，160,170,170V，180,180V，190,210,210W，220,220U，220V，220W，380或480）具有 低于其源极/漏极区（104或264）的垂直掺杂剂分布，用于减小源极/漏极区与邻接体材料（108或268）之间的pn结的寄生电容。 特别地，限定主体材料的导电类型的半导体掺杂剂的浓度在从该源极/漏极区向下移动到下面的主体材料位置时不小于10倍深度的上方增加至少10倍 半导体表面比该源/漏区。 主体材料优选地包括沿着另一个源极/漏极区（102或262）设置的更重掺杂的凹穴部分（120或280）。 通常用作漏极的第一提及的源极/漏极区下方的低破坏垂直掺杂物分布以及通常用作源的第二次提供的源极/漏极区的凹穴部分的组合使得所得的不对称晶体管能够 特别适用于高速模拟应用。