PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF
    42.
    发明申请
    PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF 有权
    印刷电路板及其制造方法

    公开(公告)号:US20120073861A1

    公开(公告)日:2012-03-29

    申请号:US13235110

    申请日:2011-09-16

    CPC classification number: H05K3/4644 H05K1/0271 H05K2201/09036

    Abstract: A printed circuit board and a manufacturing method of the printed circuit board are disclosed. The printed circuit board includes: a first insulation layer having a first pattern formed thereon; a first trench caved in one surface of the first insulation layer along at least a portion of the first pattern; and a second insulation layer stacked on one surface of the first insulation layer so as to cover the first pattern. The first trench is filled by the second insulation layer.

    Abstract translation: 公开了印刷电路板和印刷电路板的制造方法。 印刷电路板包括:第一绝缘层,其上形成有第一图案; 沿着所述第一图案的至少一部分在所述第一绝缘层的一个表面中凹陷的第一沟槽; 以及层叠在所述第一绝缘层的一个表面上以覆盖所述第一图案的第二绝缘层。 第一沟槽由第二绝缘层填充。

    DISPLAY APPARATUS
    43.
    发明申请
    DISPLAY APPARATUS 有权
    显示设备

    公开(公告)号:US20110126440A1

    公开(公告)日:2011-06-02

    申请号:US12951343

    申请日:2010-11-22

    Abstract: Disclosed is a display apparatus including a first case and a second case coupled to each other to define an external appearance of the display apparatus. A fastening guide extends from an inner surface of the first case, and a fastening member is engaged with the fastening guide. The fastening member is provided with a boss portion for screw-fastening. The first case and second case are coupled to each other using the fastening guide and fastening member having a thin thickness, whereby a reduced thickness of fastening parts and stable inter-coupling of the first case and second case are accomplished.

    Abstract translation: 公开了一种显示装置,包括彼此耦合以限定显示装置的外观的第一壳体和第二壳体。 紧固引导件从第一壳体的内表面延伸,并且紧固构件与紧固引导件接合。 紧固构件设置有用于螺纹紧固的凸台部。 第一壳体和第二壳体使用具有薄的厚度的紧固引导件和紧固构件彼此联接,从而实现第一壳体和第二壳体的紧固部件的减小的厚度和稳定的互连。

    Input buffer for detecting an input signal
    44.
    发明授权
    Input buffer for detecting an input signal 失效
    用于检测输入信号的输入缓冲器

    公开(公告)号:US07948272B2

    公开(公告)日:2011-05-24

    申请号:US10990412

    申请日:2004-11-18

    CPC classification number: H03K19/003

    Abstract: An input buffer which detects an input signal. The input buffer including an output node, a first buffer, and a second buffer. The first buffer may control the voltage level of the output node when the voltage level of a reference voltage signal is equal to a predetermined voltage level. The second buffer may control the voltage level of the output node in response to the input signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level. The second buffer may maintain the output node at a first level. The second buffer may include an output control section and a level control unit. The output control section may receive the input signal and generate a level output signal at a second level. The level control section may generate a control signal which maintains the output node at the first level, in response to the level output signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level of the first voltage and may intercept the control signal when the voltage level of the reference voltage signal is equal to the predetermined voltage level.

    Abstract translation: 输入缓冲器,用于检测输入信号。 输入缓冲器包括输出节点,第一缓冲器和第二缓冲器。 当参考电压信号的电压电平等于预定电压电平时,第一缓冲器可以控制输出节点的电压电平。 当参考电压信号的电压电平低于预定电压电平时,第二缓冲器可以响应于输入信号来控制输出节点的电压电平。 第二缓冲器可以将输出节点维持在第一级。 第二缓冲器可以包括输出控制部分和电平控制单元。 输出控制部分可以接收输入信号并产生第二电平的电平输出信号。 当参考电压信号的电压电平低于第一电压的预定电压电平时,电平控制部分可以响应于电平输出信号而产生将输出节点维持在第一电平的控制信号,并且可以拦截 当参考电压信号的电压电平等于预定电压电平时,控制信号。

    PHOTONIC CRYSTAL WAVEGUIDE INLET STRUCTURE
    45.
    发明申请
    PHOTONIC CRYSTAL WAVEGUIDE INLET STRUCTURE 有权
    光电晶体波导入口结构

    公开(公告)号:US20100142893A1

    公开(公告)日:2010-06-10

    申请号:US12391075

    申请日:2009-02-23

    CPC classification number: G02B6/1225 B82Y20/00

    Abstract: Disclosed herein is a photonic crystal waveguide inlet structure for improving coupling efficiency of a strip waveguide and a photonic crystal waveguide. The photonic crystal waveguide inlet structure includes an inlet region of the photonic crystal waveguide. The photonic crystal waveguide includes photonic crystals in which air holes are arranged in a triangle lattice shape in a dielectric, and a hybrid waveguide in which at least one of the air holes is removed, the hybrid waveguide spacing the inlet region apart from the strip waveguide.

    Abstract translation: 本文公开了一种用于提高条形波导和光子晶体波导的耦合效率的光子晶体波导入口结构。 光子晶体波导入口结构包括光子晶体波导的入口区域。 光子晶体波导包括其中空气孔在电介质中以三角形格子形状布置的光子晶体和其中至少一个空气孔被去除的混合波导,该混合波导将入口区域与带状波导分开 。

    On-die termination circuit, method of controlling the same, and ODT synchronous buffer
    46.
    发明申请
    On-die termination circuit, method of controlling the same, and ODT synchronous buffer 失效
    片上终端电路,控制方法和ODT同步缓冲器

    公开(公告)号:US20080204071A1

    公开(公告)日:2008-08-28

    申请号:US12071848

    申请日:2008-02-27

    Abstract: An on-die termination (ODT) circuit may include an ODT synchronous buffer and/or an ODT gate. The ODT synchronous buffer may be configured to generate a synchronous ODT command from an external ODT command in synchronization with a first clock signal delay-locked to an external clock signal. The ODT gate may be configured to generate signals for controlling ODT based on a second clock signal delay-locked to the external clock signal and the synchronous ODT command. The synchronous ODT command may be generated in a disabled period of the second clock signal.

    Abstract translation: 片上终端(ODT)电路可以包括ODT同步缓冲器和/或ODT门。 ODT同步缓冲器可以被配置为与延迟锁定到外部时钟信号的第一时钟信号同步地从外部ODT命令生成同步ODT命令。 ODT门可以被配置为基于延迟锁定到外部时钟信号和同步ODT命令的第二时钟信号来产生用于控制ODT的信号。 可以在第二时钟信号的禁用时段中生成同步ODT命令。

    Method and apparatus for compensating for disc eccentricity in optical disc servo system
    47.
    发明授权
    Method and apparatus for compensating for disc eccentricity in optical disc servo system 有权
    光盘伺服系统补偿盘偏心的方法和装置

    公开(公告)号:US07317669B2

    公开(公告)日:2008-01-08

    申请号:US10894360

    申请日:2004-07-20

    Applicant: Dong-Jin Lee

    Inventor: Dong-Jin Lee

    CPC classification number: G11B7/0953

    Abstract: A method and apparatus compensating for disc eccentricity includes extracting eccentricity data from a tracking error signal having one period, generated by a tracking servo, detecting parameter values of an eccentricity component extracted during the extraction of the eccentricity data and transforming a reference sine wave based on the detected parameter values of the eccentricity component. The eccentricity data is replaced with the transformed reference sine wave and the replaced eccentricity data is added to the tracking error signal to compensate for the disc eccentricity.

    Abstract translation: 补偿盘偏心度的方法和装置包括从跟踪伺服产生的具有一个周期的跟踪误差信号中提取偏心数据,检测在提取偏心数据期间提取的偏心分量的参数值,并基于 检测到偏心分量的参数值。 偏心率数据被变换后的参考正弦波代替,替代的偏心数据被加到跟踪误差信号中,以补偿盘偏心。

    Apparatus and method for determining disc type
    48.
    发明授权
    Apparatus and method for determining disc type 有权
    用于确定光盘类型的装置和方法

    公开(公告)号:US07274640B2

    公开(公告)日:2007-09-25

    申请号:US10229134

    申请日:2002-08-28

    Abstract: A disc type determining apparatus in a disc recording and reproducing apparatus in which vibrations generated by rotations of a disc occur in a focus and tracking control actuator includes an error gain adjusting unit, which adjusts an amplitude of a focus and tracking error in order to maintain a constant amplitude of the focus and tracking error; a loop gain adjusting unit which compares the closed loop phase of the focus and tracking control loop and a predetermined reference closed loop phase, and maintains a constant gain of the focus and tracking control loop; a vibration measuring unit which measures vibrations using the adjusted error and the output of a controller; and a disc type determining unit which extracts a predetermined signal to determine the type of a disc using the measured vibrations, measures the deflection, eccentricity, and mass eccentricity of a disc using the extracted signal.

    Abstract translation: 在光盘记录和再现装置中的光盘类型确定装置,其中在焦点和跟踪控制致动器中发生的盘的旋转产生的振动包括误差增益调节单元,其调整聚焦的幅度和跟踪误差以便维持 焦距和跟踪误差的恒定幅度; 循环增益调整单元,其比较聚焦和跟踪控制环的闭环相位和预定的参考闭环相位,并且保持聚焦和跟踪控制环路的恒定增益; 振动测量单元,其使用调整后的误差和控制器的输出来测量振动; 以及盘型确定单元,其使用所测量的振动提取预定信号以确定盘的类型,使用所提取的信号测量盘的偏转,偏心率和质量偏心率。

    OUTPUT DRIVER CAPABLE OF CONTROLLING A SHORT CIRCUIT CURRENT
    49.
    发明申请
    OUTPUT DRIVER CAPABLE OF CONTROLLING A SHORT CIRCUIT CURRENT 失效
    可控制短路电流的输出驱动器

    公开(公告)号:US20070182462A1

    公开(公告)日:2007-08-09

    申请号:US11609660

    申请日:2006-12-12

    Applicant: Dong-Jin Lee

    Inventor: Dong-Jin Lee

    Abstract: An output driver capable of controlling a short circuit current includes a driving unit and a driving control unit. The driving unit receives a first driving signal and a second driving signal in response to a control signal and generates an output signal. The driving unit control unit includes a driving unit copying unit having the same construction as the driving unit and compares an output copying signal generated from the first and second driving signals by the driving unit copying unit with a reference voltage and generates the control signal that controls delays of the first and second driving signals in a test mode.

    Abstract translation: 能够控制短路电流的输出驱动器包括驱动单元和驱动控制单元。 驱动单元响应于控制信号接收第一驱动信号和第二驱动信号,并产生输出信号。 驱动单元控制单元包括具有与驱动单元相同结构的驱动单元复制单元,并将由驱动单元复制单元产生的第一和第二驱动信号的输出复制信号与参考电压进行比较,并产生控制信号 在测试模式下第一和第二驱动信号的延迟。

    Semiconductor controlled rectifier for use in electrostatic discharge protection circuit
    50.
    发明授权
    Semiconductor controlled rectifier for use in electrostatic discharge protection circuit 有权
    半导体控制整流器用于静电放电保护电路

    公开(公告)号:US06707653B2

    公开(公告)日:2004-03-16

    申请号:US10251979

    申请日:2002-09-23

    CPC classification number: H01L27/0262

    Abstract: An electrostatic discharge (ESD) protection circuit includes an MOS transistor acting as a trigger for the circuit. A drain region of the MOS transistor is formed by an N-type heavily doped impurity region which overlaps an N-type well region. Further, a P-type heavily doped impurity region is formed in the N-type well region. The N-type and P-type heavily doped impurity regions are electrically connected to an input/output pad. The ESD protection circuit exhibits a reduced input capacitance at the pad, and a reduced breakdown voltage of the MOS transistor.

    Abstract translation: 静电放电(ESD)保护电路包括用作电路触发器的MOS晶体管。 MOS晶体管的漏极区域与N型阱区域重叠的N型重掺杂杂质区域形成。 此外,在N型阱区中形成P型重掺杂杂质区。 N型和P型重掺杂杂质区域电连接到输入/输出焊盘。 ESD保护电路在焊盘处表现出降低的输入电容,并且降低了MOS晶体管的击穿电压。

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