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    Input buffer for detecting an input signal
    1.
    发明授权
    Input buffer for detecting an input signal 失效
    用于检测输入信号的输入缓冲器

    公开(公告)号：US07948272B2

    公开(公告)日：2011-05-24

    申请号：US10990412

    申请日：2004-11-18

    申请人： Dong-jin Lee ,  Jung-bae Lee ,  Kyu-hyoun Kim

    发明人： Dong-jin Lee ,  Jung-bae Lee ,  Kyu-hyoun Kim

    IPC分类号： H03K5/22

    CPC分类号： H03K19/003

    摘要： An input buffer which detects an input signal. The input buffer including an output node, a first buffer, and a second buffer. The first buffer may control the voltage level of the output node when the voltage level of a reference voltage signal is equal to a predetermined voltage level. The second buffer may control the voltage level of the output node in response to the input signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level. The second buffer may maintain the output node at a first level. The second buffer may include an output control section and a level control unit. The output control section may receive the input signal and generate a level output signal at a second level. The level control section may generate a control signal which maintains the output node at the first level, in response to the level output signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level of the first voltage and may intercept the control signal when the voltage level of the reference voltage signal is equal to the predetermined voltage level.

    摘要翻译： 输入缓冲器，用于检测输入信号。 输入缓冲器包括输出节点，第一缓冲器和第二缓冲器。 当参考电压信号的电压电平等于预定电压电平时，第一缓冲器可以控制输出节点的电压电平。 当参考电压信号的电压电平低于预定电压电平时，第二缓冲器可以响应于输入信号来控制输出节点的电压电平。 第二缓冲器可以将输出节点维持在第一级。 第二缓冲器可以包括输出控制部分和电平控制单元。 输出控制部分可以接收输入信号并产生第二电平的电平输出信号。 当参考电压信号的电压电平低于第一电压的预定电压电平时，电平控制部分可以响应于电平输出信号而产生将输出节点维持在第一电平的控制信号，并且可以拦截 当参考电压信号的电压电平等于预定电压电平时，控制信号。

    Input buffer for detecting an input signal
    2.
    发明申请
    Input buffer for detecting an input signal 失效
    用于检测输入信号的输入缓冲器

    公开(公告)号：US20050116746A1

    公开(公告)日：2005-06-02

    申请号：US10990412

    申请日：2004-11-18

    申请人： Dong-jin Lee ,  Jung-bae Lee ,  Kyu-hyoun Kim

    发明人： Dong-jin Lee ,  Jung-bae Lee ,  Kyu-hyoun Kim

    IPC分类号： H03K19/0175 ,  H03K19/003 ,  H03B1/00

    CPC分类号： H03K19/003

    摘要： An input buffer which detects an input signal. The input buffer including an output node, a first buffer, and a second buffer. The first buffer may control the voltage level of the output node when the voltage level of a reference voltage signal is equal to a predetermined voltage level. The second buffer may control the voltage level of the output node in response to the input signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level. The second buffer may maintain the output node at a first level. The second buffer may include an output control section and a level control unit. The output control section may receive the input signal and generate a level output signal at a second level. The level control section may generate a control signal which maintains the output node at the first level, in response to the level output signal when the voltage level of the reference voltage signal is lower than the predetermined voltage level of the first voltage and may intercept the control signal when the voltage level of the reference voltage signal is equal to the predetermined voltage level.

    摘要翻译： 输入缓冲器，用于检测输入信号。 输入缓冲器包括输出节点，第一缓冲器和第二缓冲器。 当参考电压信号的电压电平等于预定电压电平时，第一缓冲器可以控制输出节点的电压电平。 当参考电压信号的电压电平低于预定电压电平时，第二缓冲器可以响应于输入信号来控制输出节点的电压电平。 第二缓冲器可以将输出节点维持在第一级。 第二缓冲器可以包括输出控制部分和电平控制单元。 输出控制部分可以接收输入信号并产生第二电平的电平输出信号。 当参考电压信号的电压电平低于第一电压的预定电压电平时，电平控制部分可以响应于电平输出信号而产生将输出节点维持在第一电平的控制信号，并且可以拦截 当参考电压信号的电压电平等于预定电压电平时，控制信号。

    Signal transmission circuit and method for equalizing disparate delay times dynamically, and data latch circuit of semiconductor device implementing the same
    3.
    发明授权
    Signal transmission circuit and method for equalizing disparate delay times dynamically, and data latch circuit of semiconductor device implementing the same 失效
    用于动态均衡延迟时间的信号传输电路和方法，以及实现相同延迟时间的半导体器件的数据锁存电路

    公开(公告)号：US07085336B2

    公开(公告)日：2006-08-01

    申请号：US09875364

    申请日：2001-06-05

    申请人： Jung-bae Lee ,  Kyu-hyoun Kim

    发明人： Jung-bae Lee ,  Kyu-hyoun Kim

    IPC分类号： H04L7/00

    CPC分类号： H04L1/22 ,  H04L25/14

    摘要： A signal transmission circuit and a method equalize differential delay characteristics of two signal transmission lines. A controllable delay unit is connected serially to the second line, so as to compensate by adding its internal delay. An auxiliary signal transmission line replicates the second transmission line, while it processes the input signal of the first. A controlling unit compares the output signal of the first transmission line and the of the auxiliary signal transmission line, and adjusts dynamically the internal delay of the controllable delay unit, to attain continuous synchronization. A data latch circuit synchronizes the delays of data paths by having one controllable delay units in each of the data paths.

    摘要翻译： 信号传输电路和均衡两条信号传输线的差分延迟特性的方法。 可控延迟单元串联连接到第二线，以便通过增加其内部延迟来补偿。 辅助信号传输线在处理第一传输线的输入信号时复制第二传输线。 控制单元将第一传输线的输出信号与辅助信号传输线的输出信号进行比较，并动态地调整可控延迟单元的内部延迟，以获得连续同步。 数据锁存电路通过在每个数据路径中具有一个可控延迟单元来同步数据路径的延迟。

    Input buffer circuits with input signal boost capability and methods of operation thereof
    4.
    发明授权
    Input buffer circuits with input signal boost capability and methods of operation thereof 失效
    具有输入信号提升能力的输入缓冲电路及其操作方法

    公开(公告)号：US06414517B1

    公开(公告)日：2002-07-02

    申请号：US09685266

    申请日：2000-10-10

    申请人： Kyu-hyoun Kim ,  Jung-bae Lee

    发明人： Kyu-hyoun Kim ,  Jung-bae Lee

    IPC分类号： H03K19094

    CPC分类号： H04L25/028 ,  H04L25/0272

    摘要： An input buffer includes an amplifier circuit, such as a differential amplifier circuit, inverting amplifier circuit or pull-up/pull-down amplifier circuit. A momentary boost circuit is coupled to an input buffer input terminal, an input terminal of the amplifier circuit, and an output terminal of the amplifier circuit, and is operative to generate a boosted input signal at the input terminal of the amplifier circuit from an input signal at an input buffer input terminal for an interval that is terminated responsive to an output signal at the output terminal of the amplifier circuit. The momentary boost circuit may include a detector circuit coupled to the output terminal of the amplifier circuit and operative to generate a control signal responsive to a transition of the output signal, and a boost circuit, coupled between the input buffer input terminal and the input terminal of the amplifier circuit and operatively associated with the detector circuit, that receives the input signal at the input buffer input terminal and generates the boosted input signal at the input terminal of the amplifier circuit from the received input signal responsive to the control signal. For example, the boost circuit may include a capacitor coupled between the input buffer input terminal and the input terminal of the amplifier circuit, and a switch that couples and decouples the input terminal of the amplifier circuit to a reference voltage source responsive to the control signal. The detector circuit may be operative to generate a pulse responsive to a transition of the output signal, and the switch may be operative to couple the input terminal of the amplifier circuit to the reference voltage source responsive to the pulse.

    摘要翻译： 输入缓冲器包括诸如差分放大器电路，反相放大器电路或上拉/下拉放大器电路的放大器电路。 瞬时升压电路耦合到输入缓冲器输入端子，放大器电路的输入端子和放大器电路的输出端子，并且可操作以从放大器电路的输入端在输入端产生升压输入信号 在输入缓冲器输入端子处，响应于在放大器电路的输出端子处的输出信号而终止的间隔的信号。 瞬时升压电路可以包括耦合到放大器电路的输出端的检测器电路，并且可操作以响应于输出信号的转变而产生控制信号，以及耦合在输入缓冲器输入端和输入端之间的升压电路 并且与检测器电路可操作地相关联，其在输入缓冲器输入端子处接收输入信号，并且响应于控制信号从所接收的输入信号在放大器电路的输入端产生升压的输入信号。 例如，升压电路可以包括耦合在输入缓冲器输入端子和放大器电路的输入端子之间的电容器，以及响应于控制信号将放大器电路的输入端子耦合到参考电压源的开关 。 检测器电路可操作以响应于输出信号的转变而产生脉冲，并且开关可以用于响应于脉冲将放大器电路的输入端耦合到参考电压源。

    Methods and circuits for correcting a duty-cycle of a signal
    5.
    发明授权
    Methods and circuits for correcting a duty-cycle of a signal 有权
    用于校正信号占空比的方法和电路

    公开(公告)号：US06466071B2

    公开(公告)日：2002-10-15

    申请号：US09826566

    申请日：2001-04-05

    申请人： Kyu-hyoun Kim ,  Jung-bae Lee

    发明人： Kyu-hyoun Kim ,  Jung-bae Lee

    IPC分类号： H03K3017

    CPC分类号： H03K5/1565 ,  H03K5/133 ,  H03L7/0812 ,  H03L2207/12 ,  Y10S331/02

    摘要： A signal is duty-cycle corrected by delaying the signal to generate a delayed version of the signal and generating an output signal that transitions from a first state to a second state responsive to a transition of the signal from the first state to the second state and a transition of the delayed version of the signal from the second state to the first state. The output signal transitions from the second state to the first state responsive to a transition of the signal from the second state to the first state and a transition of the delayed version of the signal from the first state to the second state.

    摘要翻译： 通过延迟信号以产生信号的延迟版本并产生响应于信号从第一状态到第二状态的转变而从第一状态转变到第二状态的输出信号来对信号进行占空比校正， 将信号的延迟版本从第二状态转换到第一状态。 响应于信号从第二状态到第一状态的转变以及信号从第一状态到第二状态的延迟版本的转变，输出信号从第二状态转变到第一状态。

    Digital phase detector with zero phase offset
    6.
    发明授权
    Digital phase detector with zero phase offset 失效

    公开(公告)号：US08718216B2

    公开(公告)日：2014-05-06

    申请号：US13242053

    申请日：2011-09-23

    申请人： Daniel M. Dreps ,  Kyu-hyoun Kim ,  Glen A. Wiedemeier

    发明人： Daniel M. Dreps ,  Kyu-hyoun Kim ,  Glen A. Wiedemeier

    IPC分类号： H03D3/24

    CPC分类号： H04L7/0037 ,  H03L7/0814 ,  H03L7/085 ,  H03L7/089

    摘要： An embodiment of the invention comprises a digital phase detector with substantially zero phase offset. The digital phase detector receives a clock signal and a reference clock signal and provides a phase indicator signal to identify whether the clock signal leads or lags the reference clock signal. An embodiment of the invention comprises a method that adds substantially zero phase offset in processing an input clock signal and a delayed clock signal to generate a control signal. The control signal is processed in a variable delay line to generate the delayed clock signal. In an embodiment, a first processor comprises a delay locked loop having a digital phase detector, the digital phase detector comprising a first differential sense amplifier cross-coupled to a second differential sense amplifier, the digital phase detector receiving a clock signal and generating one or more delayed clock signals, a control signal, and a gated data signal.

    Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device
    7.
    发明授权
    Power management of a spare DRAM on a buffered DIMM by issuing a power on/off command to the DRAM device 失效
    通过向DRAM设备发出电源开/关命令，对缓冲DIMM上的备用DRAM进行电源管理

    公开(公告)号：US08639874B2

    公开(公告)日：2014-01-28

    申请号：US12341515

    申请日：2008-12-22

    申请人： Warren Edward Maule ,  Kevin C. Gower ,  Kyu-hyoun Kim ,  Dustin James VanStee

    发明人： Warren Edward Maule ,  Kevin C. Gower ,  Kyu-hyoun Kim ,  Dustin James VanStee

    IPC分类号： G06F12/06

    CPC分类号： G11C5/06 ,  G11C5/04 ,  G11C5/14 ,  G11C11/4074

    摘要： A computer memory, having one or more of a semiconductor memory device having an internal memory array comprising a plurality of semiconductor dynamic random access memory (DRAM) cells arranged in a matrix of rows and columns, and provided as a memory module rank of such memory devices arranged in an array on a DIMM of one or more of said semiconductor memory device on a substrate which can be coupled via a memory device data interface to a memory system as a memory subsystem, each of said memory device having a low power shut-down state that can be activated using a common memory data interface. Control of power to a DRAM issues over the data interface two commands to a DRAM power control command decode, a power-state program signal and a power-state reset signal as a power-state control commands to control the power state of said DRAM, and to activate for READ/WRITE a memory cell as a normal active or spare device.

    摘要翻译： 一种具有一个或多个具有内部存储器阵列的半导体存储器件的计算机存储器，所述内部存储器阵列包括排列成行和列的矩阵的多个半导体动态随机存取存储器（DRAM）单元，并被提供为这种存储器的存储器模块等级 在基板上的一个或多个所述半导体存储器件的DIMM上布置的阵列中的器件，其可以经由存储器件数据接口耦合到作为存储器子系统的存储器系统，每个所述存储器件具有低功率闭合 - 可以使用公共存储器数据接口激活。 通过数据接口对DRAM的功率的控制问题DRAM功率控制命令的两个命令解码，功率状态程序信号和功率状态复位信号作为功率状态控制命令来控制所述DRAM的功率状态， 并激活用于将存储器单元作为正常的有源或备用设备读/写。

    MEMORY SYSTEM WITH A PROGRAMMABLE REFRESH CYCLE
    10.
    发明申请
    MEMORY SYSTEM WITH A PROGRAMMABLE REFRESH CYCLE 有权
    具有可编程刷新周期的存储器系统

    公开(公告)号：US20120151131A1

    公开(公告)日：2012-06-14

    申请号：US12963797

    申请日：2010-12-09

    申请人： Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Vipin Patel

    发明人： Charles A. Kilmer ,  Kyu-hyoun Kim ,  Warren E. Maule ,  Vipin Patel

    IPC分类号： G06F12/00 ,  G11C11/406

    CPC分类号： G11C11/406 ,  G11C2211/4061 ,  G11C2211/4065

    摘要： A memory system with a programmable refresh cycle including a memory device that includes a memory array of memory cells and refresh circuitry that is in communication with the memory array and with a memory controller. The refresh circuitry is configured to receive a refresh command from the memory controller and for refreshing a number of the memory cells in the memory device in response to receiving the refresh command. The number of memory cells refreshed in response to receiving the refresh command is programmable.

    摘要翻译： 一种具有可编程刷新周期的存储器系统，包括存储器件，该存储器件包括与存储器阵列和存储器控制器通信的存储器单元的存储器阵列和刷新电路。 刷新电路被配置为响应于接收到刷新命令从存储器控制器接收刷新命令并且用于刷新存储器件中的多个存储器单元。 响应于接收刷新命令刷新的存储器单元的数量是可编程的。