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    Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same
    41.
    发明申请
    Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same 有权
    具有覆盖键和对准键的集成电路半导体器件及其制造方法

    公开(公告)号：US20050031995A1

    公开(公告)日：2005-02-10

    申请号：US10867468

    申请日：2004-06-14

    申请人： Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

    发明人： Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

    IPC分类号： G03F9/00 ,  G03F7/00 ,  G03F7/20 ,  H01L21/027 ,  H01L23/544

    CPC分类号： H01L23/544 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.

    摘要翻译： 一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案 硅衬底和形成在第一绝缘图案上的第一导电图案。 覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案 绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。 对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案 第二掩埋绝缘层和第三沟槽。

    PHOTOELECTRIC DEVICE
    44.
    发明申请
    PHOTOELECTRIC DEVICE 有权
    光电器件

    公开(公告)号：US20130092224A1

    公开(公告)日：2013-04-18

    申请号：US13424450

    申请日：2012-03-20

    申请人： Doo-Youl LEE ,  Young-Jin Kim ,  Dong-Seop Kim ,  Chan-Bin Mo ,  Young-Su Kim ,  Young-Sang Park

    发明人： Doo-Youl LEE ,  Young-Jin Kim ,  Dong-Seop Kim ,  Chan-Bin Mo ,  Young-Su Kim ,  Young-Sang Park

    IPC分类号： H01L31/0216

    CPC分类号： H01L31/022441 ,  H01L31/0352 ,  H01L31/0745 ,  H01L31/0747 ,  H01L31/075 ,  Y02E10/547 ,  Y02E10/548

    摘要： A photoelectric device includes a first semiconductor structure and a second semiconductor structure on a substrate, and the first semiconductor structure includes a different conductivity type from the second semiconductor structure. The photoelectric device also includes a first electrode on the first semiconductor structure and a second electrode on the second semiconductor structure, and an interlayer insulating structure adjacent to the second semiconductor structure. The interlayer insulating structure separates the first semiconductor structure from the second semiconductor structure and separates the first semiconductor structure from the second electrode.

    摘要翻译： 光电器件在衬底上包括第一半导体结构和第二半导体结构，并且第一半导体结构包括与第二半导体结构不同的导电类型。 光电器件还包括第一半导体结构上的第一电极和第二半导体结构上的第二电极以及与第二半导体结构相邻的层间绝缘结构。 层间绝缘结构将第一半导体结构与第二半导体结构分开，并将第一半导体结构与第二电极分离。

    Semiconductor device and layout method for the semiconductor device
    45.
    发明授权
    Semiconductor device and layout method for the semiconductor device 有权
    半导体器件的半导体器件和布局方法

    公开(公告)号：US08339849B2

    公开(公告)日：2012-12-25

    申请号：US12498833

    申请日：2009-07-07

    申请人： Pan-suk Kwak ,  Doo-youl Lee

    发明人： Pan-suk Kwak ,  Doo-youl Lee

    IPC分类号： G11C11/34 ,  G11C16/34

    CPC分类号： H01L27/0203 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573

    摘要： Provided is a semiconductor device comprising: a plurality of bit line patterns; a plurality of pad patterns that are respectively connected to the plurality of bit line patterns; and at least one contact that is formed on each of the plurality of pad patterns, wherein the pitch of the plurality of pad patterns is greater than the pitch of the plurality of bit line patterns. The bit line patterns may be formed using a double patterning technology (DPT).

    摘要翻译： 提供一种半导体器件，包括：多个位线图案; 分别连接到所述多个位线图案的多个焊盘图案; 以及形成在所述多个焊盘图案中的每一个上的至少一个触点，其中所述多个焊盘图案的间距大于所述多个位线图案的间距。 位线图案可以使用双重图案化技术（DPT）形成。

    Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same
    47.
    发明授权
    Integrated circuit semiconductor device with overlay key and alignment key and method of fabricating the same 有权
    具有覆盖键和对准键的集成电路半导体器件及其制造方法

    公开(公告)号：US08080886B2

    公开(公告)日：2011-12-20

    申请号：US12111651

    申请日：2008-04-29

    申请人： Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

    发明人： Chang-Jin Kang ,  Myeong-Cheol Kim ,  Man-Hyoung Ryoo ,  Si-Hyeung Lee ,  Doo-Youl Lee

    IPC分类号： H01L23/544

    CPC分类号： H01L23/544 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated circuit semiconductor device including a cell region formed in a first portion of a silicon substrate, the cell region including a first trench formed in the silicon substrate, a first buried insulating layer filled in the first trench, a first insulating pattern formed over the silicon substrate, and a first conductive pattern formed over the first insulating pattern. An overlay key region is formed in a second portion of the silicon substrate and includes a second trench formed in the silicon substrate, a second insulating pattern formed over the silicon substrate and used as an overlay key, and a second conductive pattern formed over the second insulating pattern and formed by correcting overlay and alignment errors using the second insulating pattern. An alignment key region is formed in a third portion of the silicon substrate and includes a third trench formed in the silicon substrate and used as an alignment key, a second buried insulating layer formed in the third trench, and a third conductive pattern formed over the second buried insulating layer and the third trench.

    摘要翻译： 一种集成电路半导体器件，包括形成在硅衬底的第一部分中的单元区域，所述单元区域包括形成在所述硅衬底中的第一沟槽，填充在所述第一沟槽中的第一掩埋绝缘层，形成在所述第一沟槽上的第一绝缘图案 硅衬底和形成在第一绝缘图案上的第一导电图案。 覆盖键区域形成在硅衬底的第二部分中，并且包括在硅衬底中形成的第二沟槽，形成在硅衬底上并用作覆盖键的第二绝缘图案，以及形成在第二衬底上的第二导电图案 绝缘图案，并且通过使用第二绝缘图案校正覆盖和对准误差而形成。 对准键区域形成在硅衬底的第三部分中，并且包括形成在硅衬底中并用作对准键的第三沟槽，形成在第三沟槽中的第二掩埋绝缘层和形成在第三沟槽上的第三导电图案 第二掩埋绝缘层和第三沟槽。

    Method of forming fine patterns of semiconductor devices using double patterning
    48.
    发明授权
    Method of forming fine patterns of semiconductor devices using double patterning 有权
    使用双重图案形成半导体器件的精细图案的方法

    公开(公告)号：US07935635B2

    公开(公告)日：2011-05-03

    申请号：US12073502

    申请日：2008-03-06

    申请人： Kyung-yub Jeon ,  Myeong-cheol Kim ,  Doo-youl Lee ,  Hak-sun Lee

    发明人： Kyung-yub Jeon ,  Myeong-cheol Kim ,  Doo-youl Lee ,  Hak-sun Lee

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/31144 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

    摘要： A method of forming fine patterns of semiconductor device according to an example embodiment may include forming a plurality of multi-layered mask patterns by stacking first mask patterns and buffer mask patterns on an etch film to be etched on a substrate, forming, on the etch film, second mask patterns in spaces between the plurality of multi-layered mask patterns, removing the second mask patterns to expose upper surfaces of the first mask patterns, and forming the fine patterns by etching the etch film using the first and second mask patterns as an etch mask. This example embodiment may result in the formation of diverse dimensions at diverse pitches on a single substrate.

    摘要翻译： 根据示例性实施例的形成半导体器件的精细图案的方法可以包括通过将待蚀刻的蚀刻膜上的第一掩模图案和缓冲掩模图案堆叠在衬底上来形成多个多层掩模图案，在蚀刻 在多个多层掩模图案之间的空间中的膜，第二掩模图案，去除第二掩模图案以暴露第一掩模图案的上表面，以及通过使用第一和第二掩模图案蚀刻蚀刻膜形成精细图案作为 蚀刻掩模 该示例性实施例可以导致在单个基板上以不同间距形成不同尺寸。

    Flash memory device having improved bit-line layout and layout method for the flash memory device
    49.
    发明授权
    Flash memory device having improved bit-line layout and layout method for the flash memory device 有权
    具有改进的位线布局和闪存设备的布局方法的闪存设备

    公开(公告)号：US07804716B2

    公开(公告)日：2010-09-28

    申请号：US12222073

    申请日：2008-08-01

    申请人： Pan-suk Kwak ,  Doo-youl Lee

    发明人： Pan-suk Kwak ,  Doo-youl Lee

    IPC分类号： G11C16/06

    CPC分类号： G11C16/0483 ,  H01L27/11519

    摘要： Provided are a flash memory device having an improved bit-line layout and a layout method for the flash memory device. The flash memory device in which bit lines are disposed based on double patterning technology (DPT), may include at least one main bit line connected to a cell string including a memory cell storing data, at least one dummy bit line disposed parallel to the at least one main bit line, and a common source line transferring a common source voltage, and disposed on a different layer from a layer on which the at least one main bit line and the at least one dummy bit line are disposed, wherein the at least one dummy bit line may include a first dummy bit line transferring a first voltage and a second dummy bit line transferring a second voltage.

    摘要翻译： 提供了一种具有改进的位线布局和用于闪存设备的布局方法的闪存设备。 基于双重图案形成技术（DPT）布置位线的闪速存储器件可以包括连接到包括存储数据的存储单元的单元串的至少一个主位线，至少一个平行于at 至少一个主位线和公共源极线传输公共源电压，并且设置在与其上设置有至少一个主位线和至少一个虚拟位线的层不同的层上，其中至少 一个虚拟位线可以包括传送第一电压的第一虚拟位线和传送第二电压的第二虚拟位线。

    Semiconductor Device and Layout Method for the Semiconductor Device
    50.
    发明申请
    Semiconductor Device and Layout Method for the Semiconductor Device 有权
    半导体器件的半导体器件和布局方法

    公开(公告)号：US20100124114A1

    公开(公告)日：2010-05-20

    申请号：US12498833

    申请日：2009-07-07

    申请人： Pan-suk Kwak ,  Doo-youl Lee

    发明人： Pan-suk Kwak ,  Doo-youl Lee

    IPC分类号： G11C16/04 ,  H01L21/82 ,  H01L29/00

    CPC分类号： H01L27/0203 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11565 ,  H01L27/11573

    摘要： Provided is a semiconductor device comprising: a plurality of bit line patterns; a plurality of pad patterns that are respectively connected to the plurality of bit line patterns; and at least one contact that is formed on each of the plurality of pad patterns, wherein the pitch of the plurality of pad patterns is greater than the pitch of the plurality of bit line patterns. The bit line patterns may be formed using a double patterning technology (DPT).

    摘要翻译： 提供一种半导体器件，包括：多个位线图案; 分别连接到所述多个位线图案的多个焊盘图案; 以及形成在所述多个焊盘图案中的每一个上的至少一个触点，其中所述多个焊盘图案的间距大于所述多个位线图案的间距。 位线图案可以使用双重图案化技术（DPT）形成。