公开(公告)号：US06754287B2

公开(公告)日：2004-06-22

申请号：US09814196

申请日：2001-03-21

Applicant: Paul A. Underbrink ,  Daryush Shamlou ,  Ricke W. Clark ,  Joseph H. Colles ,  Guangming Yin ,  Patrick D. Ryan ,  Kelly H. Hale

Inventor： Paul A. Underbrink ,  Daryush Shamlou ,  Ricke W. Clark ,  Joseph H. Colles ,  Guangming Yin ,  Patrick D. Ryan ,  Kelly H. Hale

IPC: H04L2720

CPC classification number: H03F3/217 ,  H03F2200/331 ,  H04L27/2046

Abstract: Communications systems, and particularly portable personal communications systems, such as portable phones, are becoming increasingly digital. One area that has remained largely analog, however, is the modulation and RF amplifier circuits. To produce a RF frequency waveform. An output of a class D amplifier is coupled to an integrator to create an analog signal. A resonant circuit shapes an output waveform based on the analog signal to create a sinusoidal RF broadcast signal. The waveform of the class D amplifier may be duty cycle modulated. Digital modulation may occur using a digital sigma delta modulator or a digital programmable divide modulator. Using the digital modulation techniques and class D amplification techniques together allows for broadcast a PSK signal that has been decomposed into amplitude and phase components.

Abstract translation: 通信系统，特别是诸如便携式电话的便携式个人通信系统正在变得越来越数字化。 然而，仍然是模拟的一个领域是调制和RF放大器电路。 产生RF频率波形。 D类放大器的输出耦合到积分器以产生模拟信号。 谐振电路基于模拟信号对输出波形进行整形以产生正弦RF广播信号。 D类放大器的波形可以是占空比调制的。 可以使用数字Σ-Δ调制器或数字可编程分频调制器进行数字调制。 一起使用数字调制技术和D类放大技术可以广播已经分解为幅度和相位分量的PSK信号。

公开(公告)号：US06535735B2

公开(公告)日：2003-03-18

申请号：US09814921

申请日：2001-03-22

Applicant: Paul A. Underbrink ,  Daryush Shamlou ,  Ricke W. Clark ,  Joseph H. Colles ,  Guangming Yin ,  Patrick D. Ryan ,  Kelly H. Hale

Inventor： Paul A. Underbrink ,  Daryush Shamlou ,  Ricke W. Clark ,  Joseph H. Colles ,  Guangming Yin ,  Patrick D. Ryan ,  Kelly H. Hale

IPC: H04Q720

CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: Modern digital integrated circuits are commonly synchronized in their workings by clock circuits. The clock frequency for a circuit must take into account the propagation delay of signals within the critical path of the circuit. If the clock time is not adequate to allow propagation of signals through the critical path, improper circuit operation may result. The propagation delay is not a constant from circuit to circuit, and even in a single circuit may change due to temperature, power supply voltage and the like. Commonly, this variation is handled by assuming a worse case propagation delay of the critical path, and then designing the clock frequency and minimum power supply voltage of the circuit so that the circuit will function under worst case conditions. However, instead of assuming a worse case propagation delay of the critical path, the propagation delay may be measured in an actual circuit path that has been constructed to be the equivalent to, or slightly worse than, the propagation delay of the critical path. By knowing the actual worst case propagation delay, the circuit may be modified to operate with lower power supply voltages, conserving power and/or to controlling the frequency of the clock, so that the clock may be operated at or near the circuit's actual, not theoretical worst case limit. Such modifications of power supply voltage and/or clock frequency may occur during circuit operation and thus, adapt the circuit to the different operating parameters of each circuit.

公开(公告)号：US08259762B2

公开(公告)日：2012-09-04

申请号：US12857049

申请日：2010-08-16

Applicant: Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

Inventor： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

IPC: H04J3/02

CPC classification number: H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract translation: 提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

公开(公告)号：US07864909B2

公开(公告)日：2011-01-04

申请号：US12613740

申请日：2009-11-06

Applicant: Jun Cao ,  Guangming Yin

Inventor： Jun Cao ,  Guangming Yin

IPC: H04L7/00

CPC classification number: G06F1/10 ,  H03K5/135 ,  H04J3/0629 ,  H04L7/0008 ,  H04L25/14

Abstract: A signal delay structure and method of reducing skew between clock and data signals in a high-speed serial communications interface includes making a global adjustment to the clock signal in the time domain to compensate for a component of the skew that is common between the clock and all data signals. This can include skew caused by the variation in frequency of the input clock from a nominal value, misalignment between the phase of the clock and data generated at the source of the two signals. The global adjustment is made through a delay component that is common to all of the clock signal lines for which skew with data signals is to be compensated. A second level adjustment is made that compensates for the component of the skew that is common to the clock and a subset of the data signals.

Abstract translation: 在高速串行通信接口中减少时钟和数据信号之间的偏差的信号延迟结构和方法包括对时域中的时钟信号进行全局调整，以补偿时钟和 所有数据信号。 这可能包括由输入时钟从标称值的频率变化引起的偏斜，时钟相位与在两个信号的源极产生的数据之间的偏移。 通过延迟分量进行全局调整，该延迟分量对于要对其进行补偿的具有数据信号的偏斜的所有时钟信号线是共同的。 进行第二级调整，补偿时钟共同的偏斜分量和数据信号的子集。

公开(公告)号：US07834790B1

公开(公告)日：2010-11-16

申请号：US12206773

申请日：2008-09-09

Applicant: Guangming Yin

Inventor： Guangming Yin

IPC: H03M1/66

CPC classification number: H03M1/002 ,  H03M1/66

Abstract: A communication device includes a communication port that includes a digital to analog converter (DAC) that may be configured to output for transmission an analog signal that corresponds to a digital input such as link data that is to be transmitted on a physical link. The communication port further includes a control unit coupled to the DAC and may be configured to provide a bias current to the DAC during operation. In addition, the control unit may further be configured to reduce the bias current to the DAC dependent upon a mode of operation of the communication port and whether there is data to transmit.

Abstract translation: 通信设备包括通信端口，其包括数模转换器（DAC），其可以被配置为输出用于传输对应于数字输入的模拟信号，例如要在物理链路上传输的链路数据。 通信端口还包括耦合到DAC的控制单元，并且可以被配置为在操作期间向DAC提供偏置电流。 此外，控制单元还可以被配置为根据通信端口的操作模式以及是否存在要发送的数据来减小到DAC的偏置电流。

公开(公告)号：US07616725B2

公开(公告)日：2009-11-10

申请号：US10445771

申请日：2003-05-27

Applicant: Jun Cao ,  Guangming Yin

Inventor： Jun Cao ,  Guangming Yin

IPC: H04L7/00

CPC classification number: G06F1/10 ,  H03K5/135 ,  H04J3/0629 ,  H04L7/0008 ,  H04L25/14

Abstract: A signal delay structure and method of reducing skew between clock and data signals in a high-speed serial communications interface includes making a global adjustment to the clock signal in the time domain to compensate for a component of the skew that is common between the clock and all data signals. This can include skew caused by the variation in frequency of the input clock from a nominal value, misalignment between the phase of the clock and data generated at the source of the two signals. The global adjustment is made through a delay component that is common to all of the clock signal lines for which skew with data signals is to be compensated. A second level adjustment is made that compensates for the component of the skew that is common to the clock and a subset of the data signals.

Abstract translation: 在高速串行通信接口中减少时钟和数据信号之间的偏差的信号延迟结构和方法包括对时域中的时钟信号进行全局调整，以补偿时钟和 所有数据信号。 这可能包括由输入时钟从标称值的频率变化引起的偏斜，时钟相位与在两个信号的源极产生的数据之间的偏移。 通过延迟分量进行全局调整，该延迟分量对于要对其进行补偿的具有数据信号的偏斜的所有时钟信号线是共同的。 进行第二级调整，补偿时钟共同的偏斜分量和数据信号的子集。

公开(公告)号：US07449964B2

公开(公告)日：2008-11-11

申请号：US11120738

申请日：2005-05-03

Applicant: Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

Inventor： Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

IPC: H03L7/00

CPC classification number: H03L7/10 ,  H03B5/1209 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03L7/099 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.

Abstract translation: 本发明提供了一种用于基于用于调谐诸如VCO的设备内的其它设备的设置来将输出驱动器调谐到工作频率的方法。 首先将PLL和时钟电路中的VCO调谐到所需的工作频率。 此工作频率对应于离散调谐设置。 导致VCO在工作频率下工作的离散设置随后被传送到输出驱动器内的缩放放大器。 然后通过这些设置将这些驱动程序调整到工作频率。 该过程无需单独调整每个输出驱动器在工作频率下正常工作。

公开(公告)号：US20080175277A1

公开(公告)日：2008-07-24

申请号：US12014094

申请日：2008-01-15

Applicant: Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

Inventor： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

IPC: H04J3/02

CPC classification number: H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract translation: 提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

公开(公告)号：US07319706B2

公开(公告)日：2008-01-15

申请号：US10609058

申请日：2003-06-28

Applicant: Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

Inventor： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

IPC: H04J3/02

CPC classification number: H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

Abstract: The present invention provides a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

Abstract translation: 本发明提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

公开(公告)号：US07319351B2

公开(公告)日：2008-01-15

申请号：US11084369

申请日：2005-03-18

Applicant: Bo Zhang ,  Guangming Yin

Inventor： Bo Zhang ,  Guangming Yin

IPC: H03L7/06

CPC classification number: H03H11/265 ,  H03H11/126

Abstract: A delay circuit generates delayed signals. The delay circuit includes a delay locked loop having an input terminal coupled to a periodic input signal, the delay locked ioop generating one or more delayed periodic signals and a control signal for controlling the time delay between the periodic input signal and the delayed periodic signals. The delay circuit also includes a controlled delay circuit for generating one or more delayed periodic signals. The controlled delay circuit has an input terminal for receiving at least one of the delayed periodic signals from the delay locked loop and a delay control terminal coupled to the control signal from the delay locked ioop for controlling the time delay between the delayed periodic input signal received from the delay locked loop and the one or more delayed periodic signals generated by the controlled delay circuit.

Abstract translation: 延迟电路产生延迟信号。 延迟电路包括具有耦合到周期性输入信号的输入端的延迟锁定环，延迟锁定产生一个或多个延迟周期信号，以及用于控制周期性输入信号和延迟周期信号之间的时间延迟的控制信号。 延迟电路还包括用于产生一个或多个延迟周期信号的受控延迟电路。 受控延迟电路具有用于接收来自延迟锁定环路的延迟周期信号中的至少一个的输入端子和与来自延迟锁存器的控制信号耦合的延迟控制端子，用于控制接收到的延迟的周期性输入信号之间的时间延迟 从延迟锁定环和由受控延迟电路产生的一个或多个延迟周期信号。