公开(公告)号：US06909332B2

公开(公告)日：2005-06-21

申请号：US10639079

申请日：2003-08-12

申请人： Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

发明人： Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

IPC分类号： H03B5/12 ,  H03L7/099 ,  H03L7/10 ,  H04J3/04 ,  H04J3/06 ,  H04L7/00 ,  H03L7/00

CPC分类号： H03L7/10 ,  H03B5/1209 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03L7/099 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

摘要： The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.

公开(公告)号：US20050190004A1

公开(公告)日：2005-09-01

申请号：US11120738

申请日：2005-05-03

申请人： Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

发明人： Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

IPC分类号： H03B5/12 ,  H03L7/099 ,  H03L7/10 ,  H04J3/04 ,  H04J3/06 ,  H04L7/00 ,  H03B1/00

CPC分类号： H03L7/10 ,  H03B5/1209 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03L7/099 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

摘要： The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.

摘要翻译： 本发明提供了一种用于基于用于调谐诸如VCO的设备内的其它设备的设置来将输出驱动器调谐到工作频率的方法。 首先将PLL和时钟电路中的VCO调谐到所需的工作频率。 此工作频率对应于离散调谐设置。 导致VCO在工作频率下工作的离散设置随后被传送到输出驱动器内的缩放放大器。 然后通过这些设置将这些驱动程序调整到工作频率。 该过程无需单独调整每个输出驱动器在工作频率下正常工作。

公开(公告)号：US07449964B2

公开(公告)日：2008-11-11

申请号：US11120738

申请日：2005-05-03

申请人： Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

发明人： Guangming Yin ,  Bo Zhang ,  Ichiro Fujimori

IPC分类号： H03L7/00

CPC分类号： H03L7/10 ,  H03B5/1209 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03L7/099 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

摘要： The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.

摘要翻译： 本发明提供了一种用于基于用于调谐诸如VCO的设备内的其它设备的设置来将输出驱动器调谐到工作频率的方法。 首先将PLL和时钟电路中的VCO调谐到所需的工作频率。 此工作频率对应于离散调谐设置。 导致VCO在工作频率下工作的离散设置随后被传送到输出驱动器内的缩放放大器。 然后通过这些设置将这些驱动程序调整到工作频率。 该过程无需单独调整每个输出驱动器在工作频率下正常工作。

公开(公告)号：US20100306568A1

公开(公告)日：2010-12-02

申请号：US12857049

申请日：2010-08-16

申请人： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

发明人： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

IPC分类号： G06F1/04

CPC分类号： H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

摘要： Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

摘要翻译： 提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

公开(公告)号：US08750338B2

公开(公告)日：2014-06-10

申请号：US13556863

申请日：2012-07-24

申请人： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

发明人： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

IPC分类号： H04J3/02

CPC分类号： H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

摘要： Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

摘要翻译： 提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

公开(公告)号：US20120287950A1

公开(公告)日：2012-11-15

申请号：US13556863

申请日：2012-07-24

申请人： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

发明人： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

IPC分类号： H04J3/02

CPC分类号： H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

摘要： Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

摘要翻译： 提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

公开(公告)号：US07778288B2

公开(公告)日：2010-08-17

申请号：US12014094

申请日：2008-01-15

申请人： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

发明人： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

IPC分类号： H04J3/02

CPC分类号： H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

摘要： Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

摘要翻译： 提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。

公开(公告)号：US07289543B2

公开(公告)日：2007-10-30

申请号：US10778419

申请日：2004-02-13

申请人： Guangming Yin ,  Bo Zhang

发明人： Guangming Yin ,  Bo Zhang

IPC分类号： H04J3/06

CPC分类号： H04J3/04 ,  H04J3/0629 ,  H04L1/243 ,  H04L7/0008 ,  H04L25/14

摘要： A high-speed bit stream data conversion circuit receives a first bit stream(s) and recovers a clock signal from the first bit stream(s). The data conversion circuit then produces a second bit stream(s) having a second lower bit rate. A control loop adjusts the phase relationship of the recovered clock signal to the first bit stream(s) to minimize data loss when the first bit stream(s) is sliced to produce the second bit stream(s). A reference clock signal produced within a clock circuit is divided to produce a reduced frequency reference clock, which is multiplexed with a test clock signal to produce an output signal. Differentially dividing the output signal produces a series of input signals for an interpolator that selectively weighs and sums the input signals as directed by the control loop to produce the recovered clock signal with the desired phase relationship relative to the first bit stream(s).

摘要翻译： 高速比特流数据转换电路接收第一比特流并恢复来自第一比特流的时钟信号。 数据转换电路然后产生具有第二较低位速率的第二位流。 当第一比特流被分片以产生第二比特流时，控制环路将恢复的时钟信号的相位关系调整为第一比特流以最小化数据丢失。 在时钟电路内产生的参考时钟信号被分频以产生一个降低的频率参考时钟，该时钟信号与测试时钟信号多路复用以产生一个输出信号。 差分地分割输出信号产生用于内插器的一系列输入信号，其选择性地对控制环路所指示的输入信号进行加权和求和，以产生具有相对于第一位流的所需相位关系的恢复的时钟信号。

公开(公告)号：US06437720B1

公开(公告)日：2002-08-20

申请号：US09785690

申请日：2001-02-16

申请人： Guangming Yin ,  Bo Zhang

发明人： Guangming Yin ,  Bo Zhang

IPC分类号： H03M166

CPC分类号： H03M1/0663 ,  H03M1/804

摘要： A switched-capacitor digital-to-analog converter circuit is disclosed. The switched-capacitor digital-to-analog converter circuit includes crossing switches for each capacitor branch, the crossing switches are used to eliminate cross interference between digital-to-analog converter blocks sharing the same reference voltages.

摘要翻译： 公开了一种开关电容器数模转换器电路。 开关电容器数模转换器电路包括用于每个电容器分支的交叉开关，交叉开关用于消除共享相同参考电压的数模转换器模块之间的交叉干扰。

公开(公告)号：US08259762B2

公开(公告)日：2012-09-04

申请号：US12857049

申请日：2010-08-16

申请人： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

发明人： Guangming Yin ,  Bo Zhang ,  Mohammad Nejad ,  Jun Cao

IPC分类号： H04J3/02

CPC分类号： H04J3/0685 ,  H04J3/04 ,  H04J3/0629 ,  H04L7/0008

摘要： Provided is a high speed bit stream data conversion circuit that includes input ports to receive first bit streams at a first bit rate. Data conversion circuits receive the first bit streams and produce second bit stream(s), wherein the number and bit rate of the first and second bit stream(s) differ. Symmetrical pathways transport the first bit streams from the input ports to the data conversion circuits, wherein their transmission time(s) are substantially equal. A clock distribution circuit receives and symmetrically distributes a clock signal to data conversion circuits. A central trunk coupled to the clock port and located between a first pair of circuit pathways with paired branches that extend from the trunk and that couple to the data conversion circuits make up the clock distribution circuit. The distributed data clock signal latches data in data conversion circuits from the first to the second bit stream(s).

摘要翻译： 提供了一种高速比特流数据转换电路，其包括以第一比特率接收第一比特流的输入端口。 数据转换电路接收第一比特流并产生第二比特流，其中第一和第二比特流的数量和比特率不同。 对称路径将来自输入端口的第一比特流传输到数据转换电路，其中它们的传输时间基本相等。 时钟分配电路接收并对称地将时钟信号分配给数据转换电路。 耦合到时钟端口并且位于具有从主干延伸的配对分支的第一对电路路径之间的中央中继线，并且耦合到数据转换电路构成时钟分配电路。 分布式数据时钟信号将数据从第一到第二位流锁存在数据转换电路中。