ERROR-CORRECTION DECODING WITH REDUCED MEMORY AND POWER REQUIREMENTS
    41.
    发明申请
    ERROR-CORRECTION DECODING WITH REDUCED MEMORY AND POWER REQUIREMENTS 有权
    具有减少内存和电源要求的错误修正解码

    公开(公告)号:US20140164865A1

    公开(公告)日:2014-06-12

    申请号:US14236166

    申请日:2011-07-31

    IPC分类号: H03M13/11

    摘要: An example method is provided that includes receiving a representation of a codeword that includes a plurality of bits, and associating the bits with a respective plurality of one-bit hard-bit values representing the bits and multiple-bit soft-bit values representing measures of reliability of respective hard-bit values. The method includes for each of a plurality of iterations, updating a hard-bit/soft-bit value of one or more bits of a respective subset of the bits as a function of current hard-bit values of the subset's bits, and the current hard-bit and soft-bit values of the respective bit. For two iterations in which the current hard-bit and soft-bit values for each bit of a subset for both iterations is the same, the hard-bit/soft-bit value updated for any bit of the subset during one of the two iterations is the same as that computed for the respective bit during the other of the two iterations.

    摘要翻译: 提供了一种示例性方法,其包括接收包括多个比特的码字的表示,并且将比特与表示比特的相应多个一比特硬比特值和表示多个比特的度量的多比特软比特值相关联 各个硬比特值的可靠性。 该方法包括多个迭代中的每一个,作为该子集的比特的当前硬比特值的函数来更新比特的相应子集的一个或多个比特的硬比特/软比特值,以及当前 相应位的硬比特和软比特值。 对于两次迭代,其中对于两次迭代的子集的每个位的当前硬比特和软比特值是相同的,则在两次迭代之一期间为子集的任何比特更新的硬比特/软比特值 与在两次迭代中的另一个中相应位计算的相同。

    Using damping factors to overcome LDPC trapping sets
    42.
    发明授权
    Using damping factors to overcome LDPC trapping sets 有权
    使用阻尼因子来克服LDPC陷阱集

    公开(公告)号:US08504895B2

    公开(公告)日:2013-08-06

    申请号:US12489576

    申请日:2009-06-23

    IPC分类号: G11C29/00

    摘要: To decode a representation, imported from a channel, of a codeword that encodes K information bits as N>K codeword bits, estimates of the codeword bits are updated by exchanging messages between N bit nodes and N−K check nodes of a graph in a plurality of iterations. In each of one or more of the iterations, some or all values associated with the bit nodes, and/or some or all values associated with check nodes, and/or some or all messages are modified in a manner that depends explicitly on the ordinality of the iteration and is independent of any other iteration. Alternatively, the modifications are according to respective locally heteromorphic rules.

    摘要翻译: 为了解码从信道导入的代码字,其将K个信息比特编码为N> K个码字比特,通过在多个比特中的图的N个比特节点和NK个校验节点之间交换消息来更新码字比特的估计 迭代。 在一个或多个迭代中的每一个中,与位节点相关联的一些或所有值,和/或与校验节点相关联的一些或所有值和/或某些或所有消息以明确依赖于序数的方式被修改 的迭代,并且独立于任何其他迭代。 或者,修改根据各自的本地异形规则。

    Method for page- and block based scrambling in non-volatile memory
    43.
    发明授权
    Method for page- and block based scrambling in non-volatile memory 有权
    在非易失性存储器中基于页和块的加扰的方法

    公开(公告)号:US08451658B2

    公开(公告)日:2013-05-28

    申请号:US13411261

    申请日:2012-03-02

    IPC分类号: G11C7/00

    摘要: A method and system for programming and reading data with reduced read errors in a memory device. In one approach, date to be written to the memory device is scrambled using a first pseudo random number which is generated based on a number of a page of the memory device to which the data is to be written and a second pseudo random number which is generated based on a number of a block of the memory device to which the data is to be written. This avoids bit line-to-bit line and block-to-block redundancies which can result in read errors. The data may also be scrambled based on a number of a section within a page.

    摘要翻译: 一种用于对存储器件中读取错误减少的数据进行编程和读取的方法和系统。 在一种方法中,使用基于要写入数据的存储器件的页数生成的第一伪随机数和第二伪随机数来加扰要写入存储器件的日期,第二伪随机数是 基于要写入数据的存储器件的块的数量生成。 这避免了位线对位线和块到块冗余,这可能导致读取错误。 也可以基于页面内的部分的数量来加扰数据。

    System and method of reading data using a reliability measure
    46.
    发明授权
    System and method of reading data using a reliability measure 有权
    使用可靠性测量方法读取数据的系统和方法

    公开(公告)号:US08374026B2

    公开(公告)日:2013-02-12

    申请号:US12944431

    申请日:2010-11-11

    IPC分类号: G11C11/34

    摘要: In a particular embodiment, a data storage device includes a memory array including a target memory cell and one or more other memory cells. The data storage device also includes a controller coupled to the memory array. The controller is configured to directly compute a reliability measure for at least one bit stored in the target memory cell of the memory array based on a voltage value associated with the target memory cell and based on one or more corresponding voltage values associated with each of the one or more other memory cells of the memory array.

    摘要翻译: 在特定实施例中,数据存储设备包括包括目标存储器单元和一个或多个其它存储器单元的存储器阵列。 数据存储设备还包括耦合到存储器阵列的控制器。 控制器被配置为基于与目标存储器单元相关联的电压值并且基于与目标存储器单元中的每一个相关联的一个或多个相应的电压值直接计算存储在存储器阵列的目标存储器单元中的至少一个位的可靠性度量 存储器阵列的一个或多个其它存储单元。

    Interruption criteria for block decoding
    47.
    发明授权
    Interruption criteria for block decoding 有权
    块解码中断标准

    公开(公告)号:US08370711B2

    公开(公告)日:2013-02-05

    申请号:US12646995

    申请日:2009-12-24

    IPC分类号: G06F11/00

    摘要: While decoding a representation, imported from a channel, of a codeword that encodes K information bits as N>K codeword bits, by updating estimates of the codeword bits in a plurality of iterations, the iterations are interrupted upon satisfaction of an interruption criterion that is either an order-dependent interruption criterion or an interruption criterion that includes an estimate of mutual information of the codeword and a vector that is used in the decoding iterations. Either the iterations are terminated or the iterations are resumed after one or more elements of one or more vectors used in the iterations is/are modified.

    摘要翻译: 在将通过编码K个信息比特的码字作为N> K个码字比特的码字进行解码时,通过更新多个迭代中的码字比特的估计,在满足中断标准的情况下中断迭代 无论是依赖于顺序的中断标准还是包括码字的互信息的估计和在解码迭代中使用的向量的中断标准。 在迭代中使用的一个或多个向量的一个或多个元素被修改之后,迭代终止或迭代被恢复。

    Low density parity code (LDPC) decoding for memory with multiple log likelihood ratio (LLR) decoders
    49.
    发明授权
    Low density parity code (LDPC) decoding for memory with multiple log likelihood ratio (LLR) decoders 有权
    具有多对数似然比(LLR)解码器的存储器的低密度奇偶校验码(LDPC)解码

    公开(公告)号:US08301979B2

    公开(公告)日:2012-10-30

    申请号:US12574982

    申请日:2009-10-07

    IPC分类号: G11C29/00

    摘要: Data stored in memory is decoded using iterative probabilistic decoding and multiple decoders. A first decoder attempts to decode a representation of a codeword. If the attempt is unsuccessful, a second decoder attempts to decode the representation of a codeword. The second decoder may have a lower resolution than the first decoder. Probability values such as logarithmic likelihood ratio (LLR) values may be clipped in the second decoder. This approach can overcome trapping sets while exhibiting low complexity and high performance. Further, it can be implemented on existing decoders such as those used in current memory devices.

    摘要翻译: 使用迭代概率解码和多个解码器对存储在存储器中的数据进行解码。 第一解码器尝试对码字的表示进行解码。 如果尝试不成功,则第二解码器尝试对码字的表示进行解码。 第二解码器可以具有比第一解码器更低的分辨率。 诸如对数似然比(LLR)值之类的概率值可以在第二解码器中被裁剪。 这种方法可以克服陷阱集,同时表现出低复杂性和高性能。 此外,它可以在诸如当前存储器件中使用的解码器之类的现有解码器上实现。

    Adaptive dynamic reading of flash memories
    50.
    发明授权
    Adaptive dynamic reading of flash memories 有权
    闪存的自适应动态读取

    公开(公告)号:US08289781B2

    公开(公告)日:2012-10-16

    申请号:US13031221

    申请日:2011-02-20

    IPC分类号: G11C11/34

    摘要: Each of a plurality of flash memory cells is programmed to a respective one of L≧2 threshold voltage states within a threshold voltage window. Values of parameters of threshold voltage functions are adjusted in accordance with comparisons of the threshold voltages of some or all of the cells to two or more of m≧2 threshold voltage intervals within the threshold voltage window. Reference voltages for reading the cells are selected based on the values. Alternatively, the m threshold voltage intervals span the threshold voltage window, and respective threshold voltage states are assigned to the cells based on numbers of cells whose threshold voltages are in the intervals, without re-reading the cells.

    摘要翻译: 多个闪存单元中的每一个被编程为阈值电压窗口内的L≥2个阈值电压状态中的相应一个。 根据阈值电压窗口内的一些或所有单元的阈值电压与两个或多个m≥2个阈值电压间隔的比较,来调整阈值电压函数的参数值。 基于这些值来选择用于读取单元的参考电压。 或者,m阈值电压间隔跨越阈值电压窗口,并且基于阈值电压处于间隔中的单元的数量而将各个阈值电压状态分配给单元,而不重新读取单元。