公开(公告)号：US6097066A

公开(公告)日：2000-08-01

申请号：US944823

申请日：1997-10-06

Applicant: Jian-Hsing Lee ,  Yi-Hsun Wu ,  Jiaw-Ren Shih

Inventor： Jian-Hsing Lee ,  Yi-Hsun Wu ,  Jiaw-Ren Shih

IPC: H01L27/02 ,  H01L23/62 ,  H01L29/00

CPC classification number: H01L27/0288 ,  H01L27/0251

Abstract: The structure includes a plurality of first ring shape structure formed on a semiconductor wafer to act as the gates of the MOS devices. The areas in the inner side of the first ring shape structures are drain regions. A plurality of source regions having second ring shape structures are formed around each sides the first ring shape structures. A p conductive type region is formed in the wafer adjacent to the source regions. A third ring shape structure is formed in the semiconductor wafer to surround the p+conductive type region for serving as a guard ring.

Abstract translation: 该结构包括形成在半导体晶片上以用作MOS器件的栅极的多个第一环形结构。 第一环形结构的内侧的区域是漏极区域。 具有第二环形结构的多个源区域围绕第一环形结构的每一侧形成。 在与源极区域相邻的晶片中形成p导电型区域。 在半导体晶片中形成第三环形结构，以围绕用作保护环的p +导电型区域。

公开(公告)号：US6028324A

公开(公告)日：2000-02-22

申请号：US813758

申请日：1997-03-07

Applicant: Hung-Der Su ,  Jian-Hsing Lee ,  Di-Son Kuo

Inventor： Hung-Der Su ,  Jian-Hsing Lee ,  Di-Son Kuo

IPC: H01L23/544 ,  H01L23/58 ,  H01L27/108

CPC classification number: H01L22/34 ,  H01L2924/0002

Abstract: An ensemble of test structures comprising arrays of polysilicon plate MOS capacitors for the measurement of electrical quality of the MOSFET gate insulation is described. The test structures also measure plasma damage to these gate insulators incurred during metal etching and plasma ashing of photoresist. The structures are formed, either on test wafers or in designated areas of wafers containing integrated circuit chips. One of the test structures is designed primarily to minimize plasma damage so that oxide quality, and defect densities may be measured unhampered by interface traps created by plasma exposure. Other structures provide different antenna-to-oxide area ratios, useful for assessing plasma induced oxide damage and breakdown. The current-voltage characteristics of the MOS capacitors are measured by probing the structures on the wafer, thereby providing timely process monitoring capability.

Abstract translation: 描述了包括用于测量MOSFET栅极绝缘的电气质量的多晶硅板MOS电容器阵列的测试结构的集合。 测试结构还测量在金属蚀刻和光致抗蚀剂的等离子体灰化期间引起的这些栅绝缘体的等离子体损伤。 在测试晶片上或在包含集成电路芯片的晶片的指定区域中形成结构。 其中一个测试结构主要设计为最小化等离子体损伤，从而可以通过等离子体暴露产生的界面陷阱来测量氧化物质量和缺陷密度。 其他结构提供不同的天线到氧化物面积比，可用于评估等离子体诱导的氧化物损伤和击穿。 通过探测晶片上的结构来测量MOS电容器的电流 - 电压特性，从而提供及时的过程监控能力。

公开(公告)号：US6008974A

公开(公告)日：1999-12-28

申请号：US188178

申请日：1998-11-09

Applicant: Jian-Hsing Lee ,  Yi-Hsun Wu ,  Jiaw-Ren Shih ,  Jing-Meng Liu

Inventor： Jian-Hsing Lee ,  Yi-Hsun Wu ,  Jiaw-Ren Shih ,  Jing-Meng Liu

IPC: H01L27/02 ,  H02H3/22

CPC classification number: H01L27/0251 ,  H01L27/0266

Abstract: An electrostatic discharge (ESD) protective circuit for reducing the electron-tunneling phenomena in NMOS devices. Several complementary metal oxide semiconductor (CMOS) devices act as an ESD protective circuit from being destroyed. The CMOS devices are connected to an internal circuit and a power line provide a bias voltage for the devices. The drains of the CMOS devices are connected to a pad to output a driving current. A NMOS device is connected between the internal circuit and the ESD protective circuit for protecting the NMOS devices in the circuit. As an ESD pulse is input into the ESD protective circuit, the NMOS device is then turned on by the pulse. Thus, positive charges on the gate of the NMOS devices in the ESD circuit is conducted into ground. Therefore, the NMOS device between the internal circuit and the ESD circuit can prevent the gate oxide of the NMOS device in the circuit from damage.

Abstract translation: 一种用于减少NMOS器件中的电子隧道现象的静电放电（ESD）保护电路。 几种互补金属氧化物半导体（CMOS）器件用作ESD保护电路被破坏。 CMOS器件连接到内部电路，电源线为器件提供偏置电压。 CMOS器件的漏极连接到焊盘以输出驱动电流。 NMOS器件连接在内部电路和ESD保护电路之间，用于保护电路中的NMOS器件。 由于ESD脉冲被输入到ESD保护电路中，NMOS器件然后被脉冲导通。 因此，ESD电路中的NMOS器件的栅极上的正电荷被导通到地。 因此，内部电路和ESD电路之间的NMOS器件可以防止电路中的NMOS器件的栅极氧化物损坏。

公开(公告)号：US5949717A

公开(公告)日：1999-09-07

申请号：US928217

申请日：1997-09-12

Applicant: Ming-Chou Ho ,  Juang-ker Yeh ,  Jian-Hsing Lee ,  Kuo-Reay Peng

Inventor： Ming-Chou Ho ,  Juang-ker Yeh ,  Jian-Hsing Lee ,  Kuo-Reay Peng

IPC: G11C16/16 ,  G11C16/04

CPC classification number: G11C16/16

Abstract: A method to erase data from a flash EEPROM cell while electrical charges trapped in the tunnel oxide of a flash EEPROM cell are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by first applying a first relatively high positive voltage pulse to the source of the flash EEPROM cell. Simultaneously a ground reference voltage is applied to the control gate and to the semiconductor substrate. At this same time the drain is floating. The flash EEPROM cell is then detrapped by floating the source and drain and applying a second relatively high positive voltage pulse to the semiconductor substrate. At the same time a relatively large negative voltage pulse is applied to the control gate.

Abstract translation: 在快速EEPROM单元的隧道氧化物中捕获电荷的同时消除闪存EEPROM单元中的数据的方法，以在扩展的编程和擦除周期之后保持编程的阈值电压和擦除的阈值电压的适当分离。 擦除快闪EEPROM单元的方法首先是将第一相对较高的正电压脉冲施加到闪速EEPROM单元的源。 同时，对控制栅极和半导体衬底施加接地参考电压。 在同一时间，排水沟漂浮。 然后通过漂浮源极和漏极并将第二相对高的正电压脉冲施加到半导体衬底来去除快闪EEPROM单元。 同时，向控制栅极施加相当大的负电压脉冲。

公开(公告)号：US5898205A

公开(公告)日：1999-04-27

申请号：US891381

申请日：1997-07-11

Applicant: Jian-Hsing Lee

Inventor： Jian-Hsing Lee

IPC: H01L27/02 ,  H01L23/62

CPC classification number: H01L27/0266 ,  H01L27/0251 ,  H01L2924/0002

Abstract: An apparatus and method are disclosed for enhancing the operation of ESD protective circuits in a VLSI chip, having first and second CMOS devices therein which prevent damage due to ESD events, the first device being connected between a Vss contact and an I/O Pad contact and the second device being connected between a Vcc contact and the I/O Pad contact, and including diffusions in the chip that form a first diode which turns ON when negative ESD stresses develops between one of the first and second contacts and the I/O Pad contact, and which form a NPN transistor and a second diode that turn ON when positive ESD stresses develop between one of the first and second contacts and the I/O Pad contact, and additionally having the Vss and Vcc sources capacitively coupled.

Abstract translation: 公开了一种用于增强VLSI芯片中的ESD保护电路的操作的装置和方法，其具有防止由于ESD事件引起的损坏的第一和第二CMOS器件，第一器件连接在Vss触点和I / O焊盘触点 并且第二装置连接在Vcc触点和I / O焊盘触点之间，并且包括形成第一二极管的芯片中的扩散，当在第一和第二触点之间产生负ESD应力时，该二极管导通，并且I / O 并且其形成NPN晶体管和第二二极管，当在第一和第二触点之间的一个和I / O焊盘触点之间产生正的ESD应力时，该NPN晶体管和第二二极管导通，并且还具有电容耦合的Vss和Vcc源。

公开(公告)号：US5872379A

公开(公告)日：1999-02-16

申请号：US891462

申请日：1997-07-10

Applicant: Jian-Hsing Lee

Inventor： Jian-Hsing Lee

IPC: H01L27/02 ,  H01L23/62

CPC classification number: H01L27/0262 ,  H01L27/0251 ,  H01L29/7436 ,  H01L2924/0002

Abstract: An apparatus and method are disclosed for enhancing the operation of an ESD protective circuit in a VLSI chip with a combination of elements for an SCR that lower the turn-on voltage of the SCR below the oxide breakdown voltage of the CMOS devices in the VLSI circuits. A low voltage trigger source is provided for the SCR by forming an N+-P-LDD junction between the SCR and a CMOS device incorporated therein. The prior art N-channel device used in triggering the known LVTSCR is modified by removing the rate electrode and thin oxide and implanting, adjacent the N+ drain region, a P-type lightly doped drain (P-LDD) region in the substrate to form the N+-P-L.DD junction. The turn-on voltage of this N+-P-LDD junction can be made lower than the oxide breakdown voltage of the CMOS devices by adjusting the P-LDD dosage. Junction breakdown causes a forward bias resulting in turn ON of the PNP bipolar device followed by turn ON of the interconnected NPN bipolar device to produce the high current flow through the SCR. Concern about damage to the gate oxide of the prior art NMOS is obviated as there is no longer a gate oxide.

Abstract translation: 公开了一种用于增强VLSI芯片中的ESD保护电路的操作的装置和方法，其具有用于SCR的元件的组合，其将SCR的导通电压降低到VLSI电路中的CMOS器件的氧化物击穿电压以下 。 通过在SCR和其中并入的CMOS器件之间形成N + -P-LDD结，为SCR提供低电压触发源。 用于触发已知LVTSCR的现有技术N沟道器件通过移除速率电极和薄氧化物并在衬底附近与N +漏极区域相邻注入P型轻掺杂漏极（P-LDD）区域而被修改，以形成 N + -PL.DD结。 通过调节P-LDD剂量，可使该N + -P-LDD结的导通电压低于CMOS器件的氧化物击穿电压。 结点故障导致正向偏置导致PNP双极器件导通，随后互连NPN双极器件导通，以产生通过SCR的高电流。 由于不再存在栅极氧化物，所以关心对现有技术NMOS的栅极氧化物的损坏。

公开(公告)号：US5828605A

公开(公告)日：1998-10-27

申请号：US949945

申请日：1997-10-14

Applicant: Kuo-Reay Peng ,  Jian-Hsing Lee ,  Juang-Ke Yeh ,  Ming-Chon Ho

Inventor： Kuo-Reay Peng ,  Jian-Hsing Lee ,  Juang-Ke Yeh ,  Ming-Chon Ho

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14

Abstract: The present invention provides method to erase flash EEPROMS devices using a positive sine waveform (Vs) and negative Vg that drives a cell in to snapback breakdown to remove trapped electron in the tunnel oxide and improve device performance. The snapback breakdown operation of one cell in the array lowers the tunnel oxide electric field for all cells in the array. The snapback breakdown generates a substrate current that reduces the electric field thereby reducing electron and hole trapping. The method comprises the steps of: (a) applying a positive sine waveform voltage (Vs) to a source region of said EEPROM device during an entire erase cycle; (b) grounding a well region of said EEPROM device during an entire erase cycle; (c) grounding a drain region of said EEPROM device during an entire erase cycle; (d) simultaneously applying a negative voltage (Vg) to a control gate of said EEPROM device during the entire erase cycle; and whereby the positive sine waveform to the source region reduce the electric field in a tunnel oxide layer which reduces the electron and hole trapping.

Abstract translation: 本发明提供了使用正正弦波形（Vs）和负Vg擦除闪存EEPROMS器件的方法，该Vg驱动单元进行快速击穿以去除隧道氧化物中的俘获电子并提高器件性能。 阵列中的一个单元的快速恢复击穿操作降低阵列中所有单元的隧道氧化物电场。 回跳击穿产生衬底电流，其减小电场，从而减少电子和空穴捕获。 该方法包括以下步骤：（a）在整个擦除周期期间将正弦波电压（Vs）施加到所述EEPROM器件的源极区; （b）在整个擦除周期期间使所述EEPROM器件的阱区域接地; （c）在整个擦除周期期间使所述EEPROM器件的漏极区域接地; （d）在整个擦除周期期间同时向所述EEPROM器件的控制栅极施加负电压（Vg）; 并且由此向源极区域的正弦波形减小隧道氧化物层中的电场，从而减少电子和空穴捕获。

公开(公告)号：US09362384B2

公开(公告)日：2016-06-07

申请号：US14559542

申请日：2014-12-03

Applicant: Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

Inventor： Tzu-Cheng Kao ,  Jian-Hsing Lee ,  Jin-Lian Su ,  Huan-Ping Chu ,  Hung-Der Su

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/66681 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7835

Abstract: The present invention discloses a double diffused metal oxide semiconductor (DMOS) device and a manufacturing method thereof. The DMOS device includes: a first conductive type substrate, a second conductive type high voltage well, a gate, a first conductive type body region, a second conductive type source, a second conductive type drain, a first conductive type body electrode, and a first conductive type floating region. The floating region is formed in the body region, which is electrically floating and is electrically isolated from the source and the gate, such that the electrostatic discharge (ESD) effect is mitigated.

公开(公告)号：US07518843B2

公开(公告)日：2009-04-14

申请号：US11134539

申请日：2005-05-19

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC: H02H9/00 ,  H02H3/22

CPC classification number: H01L27/0262

Abstract: An ESD protection circuit includes a silicon controlled rectifier coupled between a circuit pad and ground for bypassing an ESD current from the circuit pad during an ESD event. An MOS transistor, having a source shared with the silicon controlled rectifier, is coupled between the pad and ground for reducing a trigger voltage of the silicon controlled rectifier during the ESD event. The silicon controlled rectifier has a first diode serially connected to a second diode in an opposite direction, between the pad and the shared source of the MOS transistor, for functioning as a bipolar transistor. In a layout view, a first area for placement of the first and second diodes is interposed between at least two separate sets of second areas for placement of the MOS transistor.

Abstract translation: ESD保护电路包括耦合在电路焊盘和地之间的可控硅整流器，用于在ESD事件期间旁路来自电路板的ESD电流。 具有与可控硅整流器共享的源极的MOS晶体管耦合在焊盘和地之间，以在ESD事件期间降低可控硅整流器的触发电压。 可控硅整流器具有在与MOS晶体管的焊盘和共享源之间的相反方向上串联连接到第二二极管的第一二极管，用作双极晶体管。 在布局图中，用于放置第一和第二二极管的第一区域介于至少两个分开的第二区域组之间，用于放置MOS晶体管。

公开(公告)号：US07518192B2

公开(公告)日：2009-04-14

申请号：US10985532

申请日：2004-11-10

Applicant: Kuo-Feng Yu ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu Chin Yang

Inventor： Kuo-Feng Yu ,  Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Fu Chin Yang

IPC: H01L23/62

CPC classification number: H01L21/76816 ,  H01L27/0274 ,  H01L29/78

Abstract: A semiconductor structure for electrostatic discharge protection is presented. The semiconductor structure comprises a grounded gate nMOS (GGNMOS) having a substrate, a gate electrode, a source region and a drain region. A plurality of contact plugs is formed on the source and drain side. A plurality of first level vias is electrically coupled to the GGNMOS and has a substantially asymmetrical layout in the source and drain regions. A second level via(s) re-routes the ESD current to the desired first level vias. The uniformity of the current flow in the GGNMOS is improved.

Abstract translation: 提出了一种用于静电放电保护的半导体结构。 半导体结构包括具有衬底，栅极电极，源极区域和漏极区域的接地栅极nMOS（GGNMOS）。 在源极和漏极侧形成多个接触插塞。 多个第一级通孔电耦合到GGNMOS并且在源极和漏极区域中具有基本不对称的布局。 第二级通过将ESD电流重新路由到期望的第一级通孔。 GGNMOS中电流的均匀性得到改善。