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公开(公告)号：US20110320790A1
公开(公告)日：2011-12-29
申请号：US13212654
申请日：2011-08-18
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/30054 , G06F9/3806 , G06F9/3863
摘要： Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining an incrementing tag register which is incremented by each link stack write instruction entering the pipeline, and a snapshot of the incrementing tag register, associated with each branch instruction. When a branch is evaluated and determined to have been mispredicted, the snapshot associated with it is compared to the incrementing tag register. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack, thus corrupting the link stack. The prior link address is restored to the link stack from the link stack restore buffer.
摘要翻译： 每当链接地址被写入链接堆栈时，链接堆栈条目的先前值被保存，并且在错误预测的分支之后推测地执行链路堆叠推送操作之后被还原到链路栈。 通过保持由进入管线的每个链路堆栈写入指令递增的递增标签寄存器以及与每个分支指令相关联的递增标签寄存器的快照来检测该条件。 当分支被评估并被确定为被错误预测时，将与之相关联的快照与增量标签寄存器进行比较。 一个差异表示在错误预测的分支指令之后推测发布了一个链路堆栈写入指令，并将链路地址推送到链路堆栈上，从而破坏了链路堆栈。 链路堆栈恢复缓冲区中的链路栈恢复到先前的链路地址。
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公开(公告)号：US20110219220A1
公开(公告)日：2011-09-08
申请号：US13108227
申请日：2011-05-16
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3806 , G06F9/3861
摘要： Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining a count of the total number of uncommitted link stack write instructions in the pipeline, and a count of the number of uncommitted link stack write instructions ahead of each branch instruction. When a branch is evaluated and determined to have been mispredicted, the count associated with it is compared to the total count. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack. The prior link address is restored to the link stack from the link stack restore buffer.
摘要翻译： 每当链接地址被写入链接堆栈时，链接堆栈条目的先前值被保存，并且在错误预测的分支之后推测地执行链路堆叠推送操作之后被还原到链路栈。 通过维持流水线中未提交的链路堆栈写入指令的总数的计数以及每个分支指令之前的未提交的链路栈写入指令的数量的计数来检测该条件。 当分支被评估并确定为被误判时，将与之相关联的计数与总计数进行比较。 一个差异表示在错误预测的分支指令之后推测发布了一个链接堆栈写入指令，并将链路地址推送到链路堆栈上。 链路堆栈恢复缓冲区中的链路栈恢复到先前的链路地址。
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43.发明授权Method and apparatus for managing instruction flushing in a microprocessor's instruction pipeline 有权用于在微处理器指令管线中管理指令冲洗的方法和装置公开(公告)号：US07949861B2
公开(公告)日：2011-05-24
申请号：US11149773
申请日：2005-06-10
CPC分类号： G06F9/3861 , G06F9/30072 , G06F9/3867 , G06F12/0855 , G06F12/0862 , G06F2212/6028
摘要： In one or more embodiments, a processor includes one or more circuits to flush instructions from an instruction pipeline on a selective basis responsive to detecting a branch misprediction, such that those instructions marked as being dependent on the branch instruction associated with the branch misprediction are flushed. Thus, the one or more circuits may be configured to mark instructions fetched into the processor's instruction pipeline(s) to indicate their branch prediction dependencies, directly or indirectly detect incorrect branch predictions, and directly or indirectly flush instructions in the instruction pipeline(s) that are marked as being dependent on an incorrect branch prediction.
摘要翻译： 在一个或多个实施例中，处理器包括一个或多个电路，用于响应于检测到分支错误预测而选择性地刷新来自指令流水线的指令，使得标记为依赖于与分支错误预测相关联的分支指令的那些指令被刷新 。 因此，一个或多个电路可以被配置为标记被提取到处理器的指令流水线中以指示其分支预测依赖性的指令，直接或间接地检测不正确的分支预测，以及直接或间接地刷新指令流水线中的指令， 被标记为依赖于不正确的分支预测。
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公开(公告)号：US07761774B2
公开(公告)日：2010-07-20
申请号：US11262063
申请日：2005-10-28
IPC分类号： G11C29/00
CPC分类号： G11C15/00 , G06F12/1027 , G06F2212/652 , G11C15/04
摘要： The search key and key fields of a CAM in a cache are encoded with a Hamming distance of at least two to increase the speed of the CAM by ensuring each mismatching match line is discharged by at least two transistors in parallel. Where the cache is physically tagged, the search key is a physical address. The page address portion of the physical address is encoded prior to being stored in a TLB. The page offset bits are encoded in parallel with the TLB access, and concatenated with the encoded TLB entry. If a page address addresses a large memory page size, a plurality of corresponding sub-page addresses may be generated, each addressing a smaller page size. These sub-page addresses may be encoded and stored in a micro TLB. The encoded key and key field are tolerant of single-bit soft errors.
摘要翻译： 高速缓存中的CAM的搜索键和关键字段通过至少两个汉明距离进行编码，以通过确保每个不匹配的匹配线由并联的至少两个晶体管放电来增加CAM的速度。 在缓存物理标记的地方，搜索关键字是物理地址。 物理地址的页地址部分在被存储在TLB中之前被编码。 页面偏移位与TLB访问并行编码，并与编码的TLB条目连接。 如果页面地址满足大的存储器页面大小，则可以生成多个对应的子页面地址，每个地址寻址较小的页面大小。 这些子页地址可以被编码并存储在微型TLB中。 编码的密钥和密钥字段容忍单位软错误。
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公开(公告)号：US07752396B2
公开(公告)日：2010-07-06
申请号：US12196705
申请日：2008-08-22
申请人： James Norris Dieffenderfer , Praveen G. Karandikar , Michael Bryan Mitchell , Thomas Philip Speier , Paul Michael Steinmetz
发明人： James Norris Dieffenderfer , Praveen G. Karandikar , Michael Bryan Mitchell , Thomas Philip Speier , Paul Michael Steinmetz
CPC分类号： G06F12/0833
摘要： Embodiments include a cache controller adapted to determine whether a memory line for which the processor is to issue an address-only kill request resides in a fill buffer for the cache line in a shared state. If so, the cache controller may mark the fill buffer as not having completed bus transactions and issue the address-only kill request for that fill buffer. The address-only kill request may transmit to other processors on the bus and the other processors may respond by invalidating the cache entries for the memory line. Upon confirmation from the other processors, a bus arbiter may confirm the kill request, promoting the memory line already in that fill buffer to exclusive state. Once promoted, the fill buffer may be marked as having completed the bus transactions and may be written into the cache.
摘要翻译： 实施例包括高速缓存控制器，其适于确定处理器将要发出仅地址杀死请求的存储器线是否驻留在共享状态下的高速缓存行的填充缓冲器中。 如果是这样，高速缓存控制器可以将填充缓冲区标记为没有完成总线事务并且发出针对该填充缓冲区的仅地址杀死请求。 只有地址的中断请求可以发送到总线上的其他处理器，而其他处理器可以通过使存储器线的高速缓存条目无效来进行响应。 在其他处理器确认之后，总线仲裁器可以确认杀死请求，将已经在该填充缓冲器中的存储器线路推送到独占状态。 一旦被提升，填充缓冲器可以被标记为完成总线事务并且可以被写入高速缓存。
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46.发明授权公开(公告)号：US07650466B2
公开(公告)日：2010-01-19
申请号：US11233575
申请日：2005-09-21
申请人： Brian Michael Stempel , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Robert Douglas Clancy , Victor Roberts Augsburg
发明人： Brian Michael Stempel , James Norris Dieffenderfer , Jeffrey Todd Bridges , Thomas Andrew Sartorius , Rodney Wayne Smith , Robert Douglas Clancy , Victor Roberts Augsburg
IPC分类号： G06F12/00
CPC分类号： G06F12/126
摘要： A method of managing cache partitions provides a first pointer for higher priority writes and a second pointer for lower priority writes, and uses the first pointer to delimit the lower priority writes. For example, locked writes have greater priority than unlocked writes, and a first pointer may be used for locked writes, and a second pointer may be used for unlocked writes. The first pointer is advanced responsive to making locked writes, and its advancement thus defines a locked region and an unlocked region. The second pointer is advanced responsive to making unlocked writes. The second pointer also is advanced (or retreated) as needed to prevent it from pointing to locations already traversed by the first pointer. Thus, the pointer delimits the unlocked region and allows the locked region to grow at the expense of the unlocked region.
摘要翻译： 管理高速缓存分区的方法提供用于较高优先级写入的第一指针和用于较低优先级写入的第二指针，并且使用第一指针来划分较低优先级的写入。 例如，锁定的写入具有比解锁的写入更高的优先级，并且第一指针可以用于锁定的写入，并且第二指针可以用于解锁的写入。 响应于锁定写入，第一指针是高级的，并且其进步因此定义了锁定区域和解锁区域。 响应于解锁写入，第二个指针是高级的。 第二个指针也根据需要进行高级（或撤销），以防止它指向已经被第一个指针所遍历的位置。 因此，指针限定未锁定区域，并允许锁定区域以解锁区域为代价而增长。
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公开(公告)号：US07624254B2
公开(公告)日：2009-11-24
申请号：US11626443
申请日：2007-01-24
申请人： Rodney Wayne Smith , James Norris Dieffenderfer , Michael Scott McIlvaine , Thomas Andrew Sartorius
发明人： Rodney Wayne Smith , James Norris Dieffenderfer , Michael Scott McIlvaine , Thomas Andrew Sartorius
IPC分类号： G06F9/38
CPC分类号： G06F9/384 , G06F9/3842 , G06F9/3863 , G06F9/3867
摘要： A processor pipeline is segmented into an upper portion—prior to instructions going out of program order—and one or more lower portions beyond the upper portion. The upper pipeline is flushed upon detecting that a branch instruction was mispredicted, minimizing the delay in fetching of instructions from the correct branch target address. The lower pipelines may continue execution until the mispredicted branch instruction confirms, at which time all uncommitted instructions are flushed from the lower pipelines. Existing exception pipeline flushing mechanisms may be utilized, by adding a mispredicted branch identifier, reducing the complexity and hardware cost of flushing the lower pipelines.
摘要翻译： 处理器管线在分配给程序顺序之外的指令之前被分割成上部，并且超出上部的一个或多个下部。 在检测到分支指令被错误预测时，上级流水线被刷新，从而使得从正确的分支目标地址获取指令的延迟最小化。 较低的管道可以继续执行，直到错误预测的分支指令确认，此时所有未提交的指令都从较低管道冲洗。 可以通过添加错误的分支标识符来减少冲洗下层管道的复杂性和硬件成本，来利用现有的异常流水线冲洗机制。
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48.发明授权公开(公告)号：US07617387B2
公开(公告)日：2009-11-10
申请号：US11535536
申请日：2006-09-27
申请人： Rodney Wayne Smith , Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius
发明人： Rodney Wayne Smith , Brian Michael Stempel , James Norris Dieffenderfer , Thomas Andrew Sartorius
CPC分类号： G06F9/3885 , G06F9/30058 , G06F9/3844 , G06F9/3861
摘要： A method of resolving simultaneous branch predictions prior to validation of the predicted branch instruction is disclosed. The method includes processing two or more predicted branch instructions, with each predicted branch instruction having a predicted state and a corrected state. The method further includes selecting one of the corrected states. Should one of the predicted branch instructions be mispredicted, the selected corrected state is used to direct future instruction fetches.
摘要翻译： 公开了一种在预测分支指令验证之前解决同步分支预测的方法。 该方法包括处理两个或多个预测分支指令，每个预测分支指令具有预测状态和校正状态。 该方法还包括选择一个校正状态。 如果预测的分支指令之一被错误预测，则所选择的校正状态用于指示未来的指令提取。
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公开(公告)号：US20090210663A1
公开(公告)日：2009-08-20
申请号：US12434804
申请日：2009-05-04
申请人： Thomas Andrew Sartorius , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Michael Scott McIlvaine , Rodney Wayne Smith
发明人： Thomas Andrew Sartorius , Victor Roberts Augsburg , James Norris Dieffenderfer , Jeffrey Todd Bridges , Michael Scott McIlvaine , Rodney Wayne Smith
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/3804
摘要： A processor includes a conditional branch instruction prediction mechanism that generates weighted branch prediction values. For weakly weighted predictions, which tend to be less accurate than strongly weighted predictions, the power associating with speculatively filling and subsequently flushing the cache is saved by halting instruction prefetching. Instruction fetching continues when the branch condition is evaluated in the pipeline and the actual next address is known. Alternatively, prefetching may continue out of a cache. To avoid displacing good cache data with instructions prefetched based on a mispredicted branch, prefetching may be halted in response to a weakly weighted prediction in the event of a cache miss.
摘要翻译： 处理器包括产生加权分支预测值的条件分支指令预测机制。 对于弱加权预测，其倾向于比强加权预测不太准确，通过停止指令预取来节省与推测性填充和随后刷新高速缓存的功率相关联的功率。 当流水线中评估分支条件并且已知实际的下一个地址时，指令获取继续。 或者，可以从高速缓存中继续预取。 为了避免基于错误预测的分支预取的指令移位良好的高速缓存数据，预取可以响应于在高速缓存未命中的情况下的弱加权预测而停止。
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公开(公告)号：US20090094444A1
公开(公告)日：2009-04-09
申请号：US11867727
申请日：2007-10-05
IPC分类号： G06F9/312
CPC分类号： G06F9/3842 , G06F9/3806 , G06F9/3861
摘要： Whenever a link address is written to the link stack, the prior value of the link stack entry is saved, and is restored to the link stack after a link stack push operation is speculatively executed following a mispredicted branch. This condition is detected by maintaining a count of the total number of uncommitted link stack write instructions in the pipeline, and a count of the number of uncommitted link stack write instructions ahead of each branch instruction. When a branch is evaluated and determined to have been mispredicted, the count associated with it is compared to the total count. A discrepancy indicates a link stack write instruction was speculatively issued into the pipeline after the mispredicted branch instruction, and pushed a link address onto the link stack. The prior link address is restored to the link stack from the link stack restore buffer.
摘要翻译： 每当链接地址被写入链接堆栈时，链接堆栈条目的先前值被保存，并且在错误预测的分支之后推测地执行链路堆叠推送操作之后被还原到链路栈。 通过维持流水线中未提交的链路堆栈写入指令的总数的计数以及每个分支指令之前的未提交的链路栈写入指令的数量的计数来检测该条件。 当分支被评估并确定为被误判时，将与之相关联的计数与总计数进行比较。 一个差异表示在错误预测的分支指令之后推测发布了一个链接堆栈写入指令，并将链路地址推送到链路堆栈上。 链路堆栈恢复缓冲区中的链路栈恢复到先前的链路地址。
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