公开(公告)号：US20240431106A1

公开(公告)日：2024-12-26

申请号：US18749751

申请日：2024-06-21

Applicant: Kioxia Corporation

Inventor： Koichi YAMAMOTO

IPC: H10B43/27

Abstract: A semiconductor storage device includes a stacked body in which a plurality of conductive layers are stacked one layer apart from each other and which has a staircase portion in which the plurality of conductive layers have been processed into a staircase shape, a first pillar that extends in a stacking direction of the stacked body in a portion of the stacked body different from the staircase portion and forms memory cells at each intersection between the first pillar and at least a part of the plurality of conductive layers, a plurality of second pillars that are arranged with periodicity in the staircase portion and extend in the stacking direction within the stacked body, and a contact having a diameter larger than a distance between the plurality of second pillars, that is disposed in the staircase portion and that is electrically connected to one of the plurality of conductive layers.

公开(公告)号：US20240429118A1

公开(公告)日：2024-12-26

申请号：US18679697

申请日：2024-05-31

Applicant: Kioxia Corporation

Inventor： Keisuke TOKUBUCHI

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/762 ,  H01L23/00 ,  H01L23/29 ,  H01L23/498 ,  H01L23/528 ,  H01L25/065

Abstract: A semiconductor device includes: a first substrate; a second substrate provided above the first substrate, the second substrate being smaller in area than the first substrate when the second substrate is viewed from above; a first layer provided between the first substrate and the second substrate and having a first conductive pad; a second layer provided between the first layer and the second substrate and having a second conductive pad bonded to the first conductive pad; and an insulator covering each of at least one side surface of the first substrate and at least one side surface of the second substrate.

公开(公告)号：US20240428866A1

公开(公告)日：2024-12-26

申请号：US18749384

申请日：2024-06-20

Applicant: Kioxia Corporation

Inventor： Yuki INUZUKA ,  Akiyuki MURAYAMA

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/30 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor memory device includes a memory pillar; first and second conductive layers on either side of the memory pillar; third and fourth conductive layers and fifth and sixth conductive layer respectively below and above first and second conductive layers; seventh and eighth conductive layers below third and fourth conductive layers; ninth and tenth conductive layers above fifth and sixth conductive layers; memory cells formed between a respective first through tenth conductive layers and the memory pillar; and a control circuit, which applies a read voltage to the first conductive layer, a negative voltage to second, fourth, and sixth conductive layers, and a read pass voltage to other conductive layers, applies the read pass voltage to first, second, fourth, and sixth conductive layers, applies a ground voltage or lower to a first group of conductive layers, and then a ground voltage to a second group of conductive layers.

公开(公告)号：US20240427843A1

公开(公告)日：2024-12-26

申请号：US18743892

申请日：2024-06-14

Applicant: Kioxia Corporation

Inventor： Atsushi KAWASUMI

IPC: G06F17/16

Abstract: An information processing apparatus configured to detect similarity between a first vector having a plurality of elements and a second vector having a plurality of elements based on an inner product value of the first vector and the second vector, the information processing apparatus has a wiring line having a current flowing therethrough, the current being a sum of currents each corresponding to a product of a value obtained by subtracting one of the elements of the first vector from a reference value and a corresponding one of the elements of the second vector, a sense amplifier configured to sense a voltage on the wiring line, and a similarity detection circuit configured to detect the similarity based on an output signal of the sense amplifier.

公开(公告)号：US20240426605A1

公开(公告)日：2024-12-26

申请号：US18743427

申请日：2024-06-14

Applicant: Kioxia Corporation

Inventor： Taiki ITO

IPC: G01B15/04 ,  G03F1/86 ,  G03F7/00 ,  G06F30/32 ,  G06T7/00 ,  G06T7/12 ,  G06T7/50

Abstract: A pattern shape measurement method includes generating, based on shape data on a pattern being a measurement target, contour point data including pieces of position information on contour points of the pattern (e.g., mask pattern); selecting sets of pieces of position information on consecutive contour points from the contour point data and generating a plurality of items of extracted point data including the respective sets of pieces of position information on consecutive contour points; calculating, with circuitry, for each of the plurality of items of extracted point data, a determined angle formed between a marker line based on the consecutive contour points and a base line that extends in a prescribed direction in the pattern; determining a scan angle for the charged particles with respect to the pattern based on a frequency of occurrence of the determined angle; and scanning the pattern at the determined scan angle.

公开(公告)号：US12178048B2

公开(公告)日：2024-12-24

申请号：US17475685

申请日：2021-09-15

Applicant: KIOXIA CORPORATION

Inventor： Takenori Kodama

IPC: H01L27/1157 ,  H01L27/11565 ,  H01L29/66 ,  H01L29/792 ,  H01L49/02 ,  H10B43/10 ,  H10B43/35 ,  H01L29/788 ,  H10B41/10 ,  H10B41/35

Abstract: A semiconductor device includes: a semiconductor substrate; a transistor formed on the semiconductor substrate; a first insulating layer adjacent to the transistor in a first direction along a main surface of the semiconductor substrate, the first insulating layer being formed toward an inside of the semiconductor substrate; a first conductive layer connected to a gate of the transistor, a part of the first conductive layer being opposed to the first insulating layer; a second insulating layer disposed between the first insulating layer and the first conductive layer; and a first semiconductor layer disposed between the second insulating layer and the first conductive layer.

公开(公告)号：US12176044B1

公开(公告)日：2024-12-24

申请号：US18123232

申请日：2023-03-17

Applicant: Kioxia Corporation

Inventor： Eyal Nitzan ,  Avi Steiner ,  Hanan Weingarten ,  Yasuhiko Kurosawa

IPC: G11C16/34 ,  H03M13/01 ,  H03M13/11 ,  H03M13/43

Abstract: A method for reading data from an SSD, comprising: retrieving data from a target row of memory cells using initial threshold voltages; decoding the data using a first hard decision decoding stage; estimating a bit error rate (BER) of a target row of memory cells based on a distribution of threshold voltages of cells in a memory block containing the target row when the first hard decision decoding stage fails; classifying the BER of the target row based on a first BER threshold (BER-TH1); and executing a first read flow comprising at least one hard decision decoding stage if the BER is less than the BER-TH1, and executing a second read flow similar to the first read flow if the BER is greater than or equal to the BER-TH1, the second read flow skipping a hard decision decoding stage of the first read flow.

公开(公告)号：US12175110B2

公开(公告)日：2024-12-24

申请号：US18509572

申请日：2023-11-15

Applicant: KIOXIA CORPORATION

Inventor： Yuki Sasaki ,  Shinichi Kanno

IPC: G06F3/06 ,  G06F12/02

Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The controller manages validity of data in the non-volatile memory using a data map. The data map includes first fragment tables. Each of the first fragment tables stores first and second information. The first information indicates the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second information indicates the validity of a plurality of data having a predetermined size in each of entries. The controller selects a write destination block based on a size of write data to be written to the non-volatile memory by a write command from a host.

公开(公告)号：US12172194B2

公开(公告)日：2024-12-24

申请号：US18496222

申请日：2023-10-27

Applicant: KIOXIA CORPORATION

Inventor： Minako Inukai ,  Masatoshi Terayama

IPC: B08B13/00 ,  B08B3/02 ,  H01L21/67

Abstract: A substrate processing apparatus for cleaning and drying a substrate under processing, including supplying a cleaning liquid onto the substrate under processing to form a cleaning liquid layer, supplying a gas onto the substrate under processing to partially remove the cleaning liquid layer and thus generate a first dry region on the substrate under processing, expanding the first dry region to generate a second dry region by controlling the movement speed of the boundary between the cleaning liquid layer and the first dry region to be less than or equal to a predetermined speed, and further expanding the second dry region to generate a third dry region.

公开(公告)号：US20240421121A1

公开(公告)日：2024-12-19

申请号：US18734204

申请日：2024-06-05

Applicant: Kioxia Corporation

Inventor： Masayuki MIURA ,  Kazuma HASEGAWA ,  Hideko MUKAIDA ,  Kana KUDO

IPC: H01L25/065 ,  H10B80/00

Abstract: A semiconductor device according to an embodiment includes a substrate, a first stack, a second stack, a first bonding layer, a second bonding layer, a first wire, and a second wire. The first stack has a plurality of first semiconductor chips. The second stack has a plurality of second semiconductor chips. The first bonding layer is provided at a lower part of each of the plurality of first semiconductor chips. The second bonding layer is provided at a lower part of each of the plurality of second semiconductor chips. The first wire electrically connects the first semiconductor chips and the second semiconductor chips to one another. The second wire electrically connects the substrate and the second semiconductor chips. The first bonding layer provided at the lower part of the first semiconductor chip in a lowest stage has a thickness different from the thickness of the other first bonding layers.