公开(公告)号：US20120002486A1

公开(公告)日：2012-01-05

申请号：US12983124

申请日：2010-12-31

申请人： Kyoung Nam KIM

发明人： Kyoung Nam KIM

IPC分类号： G11C7/10 ,  G11C8/18

CPC分类号： G11C16/20 ,  G06F12/0246 ,  G06F2212/7206

摘要： A nonvolatile memory apparatus includes a memory device including a configuration information storage block for storing configuration data groups. A configuration information processing circuit is configured to determine majorities of configuration data groups, which are outputted from the memory device during a first period as an initial stage of a power-up operation, under the control of a first control clock signal. The configuration information processing circuit is also configured to determine majorities of configuration data groups, which are outputted from the memory device during a second period after the first period, under the control of a second control clock signal having a cycle shorter than the first control clock signal.

摘要翻译： 非易失性存储装置包括存储装置，该存储装置包括用于存储配置数据组的配置信息存储块。 配置信息处理电路被配置为在第一控制时钟信号的控制下，确定在作为上电操作的初始阶段的第一时段期间从存储器件输出的配置数据组的多数。 配置信息处理电路还被配置为在具有比第一控制时钟短的周期的第二控制时钟信号的控制下，确定在第一时段之后的第二周期期间从存储器件输出的配置数据组的多数 信号。

公开(公告)号：US08063681B2

公开(公告)日：2011-11-22

申请号：US12915830

申请日：2010-10-29

申请人： Kyoung-Nam Kim

发明人： Kyoung-Nam Kim

IPC分类号： H03L7/06

CPC分类号： G11C8/18 ,  H03L7/0812

摘要： A semiconductor integrated circuit includes a DLL controlling block configured to enable or disable an update enable signal by detecting a change in a voltage level of a phase detecting signal during a predetermined time when an operation enable signal and a threshold phase difference detecting signal are enabled, and a delay locked loop (DLL) circuit configured to generate an output clock signal by delaying and driving the reference clock signal and to control a frequency of a change in the delay amount of the reference clock signal in response to the update enable signal.

摘要翻译： 半导体集成电路包括DLL控制块，其被配置为通过在使能使能信号和阈值相位差检测信号被使能的预定时间期间检测相位检测信号的电压电平的变化来启用或禁用更新使能信号， 以及延迟锁定环（DLL）电路，被配置为通过延迟和驱动参考时钟信号来产生输出时钟信号，并且响应于更新使能信号控制参考时钟信号的延迟量的变化的频率。

公开(公告)号：US07982511B2

公开(公告)日：2011-07-19

申请号：US11647379

申请日：2006-12-29

申请人： Kyoung Nam Kim

发明人： Kyoung Nam Kim

IPC分类号： H03L7/06

CPC分类号： H03L7/0812

摘要： A delayed lock loop (DLL) circuit includes: a phase conversion control unit configured to latch an initial value of a phase comparison signal, and output the latched signal as a phase conversion control signal. A phase converting unit configured to control the phase of a delay clock on the basis of the phase conversion control signal, and transmit the controlled delay clock to a delay compensating unit.

摘要翻译： 延迟锁定环路（DLL）电路包括：相位转换控制单元，被配置为锁存相位比较信号的初始值，并输出锁存信号作为相位转换控制信号。 相位转换单元，被配置为基于相位转换控制信号来控制延迟时钟的相位，并将受控延迟时钟发送到延迟补偿单元。

公开(公告)号：US07848163B2

公开(公告)日：2010-12-07

申请号：US11824359

申请日：2007-06-29

申请人： Kyoung-Nam Kim ,  Young-Jun Ku ,  Hoon Choi

发明人： Kyoung-Nam Kim ,  Young-Jun Ku ,  Hoon Choi

IPC分类号： G11C11/063

CPC分类号： G11C7/22 ,  G11C7/222

摘要： A semiconductor memory device includes: a delay locked loop (DLL) clock buffer for buffering a system clock in response to the a buffer enable signal; a DLL circuit for generating a delay locked loop (DLL) clock by performing a delay locking operation using the buffered system clock; and a DLL clock buffer controller for generating the buffer enable signal in response to a code signal and a clock enable signal, the code signal containing information about whether to perform the delay locking operation.

摘要翻译： 半导体存储器件包括：响应于缓冲器使能信号缓冲系统时钟的延迟锁定环（DLL）时钟缓冲器; 一个DLL电路，用于通过使用缓冲的系统时钟执行延迟锁定操作来产生延迟锁定环（DLL）时钟; 以及DLL时钟缓冲器控制器，用于响应于代码信号和时钟使能信号产生缓冲器使能信号，所述代码信号包含关于是否执行延迟锁定操作的信息。

公开(公告)号：US07715253B2

公开(公告)日：2010-05-11

申请号：US12164984

申请日：2008-06-30

申请人： Kyoung-Nam Kim ,  Ho-Youb Cho

发明人： Kyoung-Nam Kim ,  Ho-Youb Cho

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/222 ,  G11C29/022 ,  G11C29/023

摘要： Semiconductor memory device and method for operating the same comprise an auxiliary driver configured to output an internal strobe signals generated corresponding to a read command as a plurality of auxiliary strobe signal in response to a control signal, wherein the auxiliary driver bypass a first output auxiliary strobe signal, and delay to output the rest of the auxiliary strobe signal among the outputted auxiliary strobe signal and a strobe signal generator for driving the auxiliary strobe signal to output the delayed auxiliary strobe signal as a data strobe signals.

摘要翻译： 半导体存储器件及其操作方法包括：辅助驱动器，被配置为响应于控制信号输出与读命令相对应的内部选通信号作为多个辅助选通信号，其中辅助驱动器绕过第一输出辅助选通 信号和延迟以输出辅助选通信号中的其余的辅助选通信号和选通信号发生器，用于驱动辅助选通信号，以输出延迟的辅助选通信号作为数据选通信号。

公开(公告)号：US20100019767A1

公开(公告)日：2010-01-28

申请号：US12372339

申请日：2009-02-17

申请人： Zang Hee CHO ,  Young Bo KIM ,  Jae Yong HAN ,  Kyoung Nam KIM ,  Jung Hwan KIM ,  Suk Min HONG

发明人： Zang Hee CHO ,  Young Bo KIM ,  Jae Yong HAN ,  Kyoung Nam KIM ,  Jung Hwan KIM ,  Suk Min HONG

IPC分类号： G01R33/32

CPC分类号： G01R33/34046 ,  G01R33/34076 ,  G01R33/3642 ,  G01R33/3664 ,  G01R33/3678 ,  G01R33/5659

摘要： An RF (radio frequency) coil assembly of a magnetic resonance imaging (MRI) system, which has a spiral-shaped coil and a plurality of sections. In one embodiment, an RF coil of a magnetic resonance imaging (MRI) system has a plurality of ring-shaped end-rings arranged vertically and a plurality of rods. Each of the rods are connected to the plurality of end-rings. Adjacent end-rings of the plurality of end-rings forms respective coil sections and each of the coil sections has switching blocks located between adjacent rods of the plurality of rods. The switching blocks are operable to control the continuity status of the plurality of rods in the respective coil section.

摘要翻译： 磁共振成像（MRI）系统的RF（射频）线圈组件，其具有螺旋形线圈和多个部分。 在一个实施例中，磁共振成像（MRI）系统的RF线圈具有垂直布置的多个环形端环和多个杆。 每个杆连接到多个端环。 多个端环的相邻端环形成相应的线圈段，并且每个线圈段具有位于多个杆的相邻杆之间的切换块。 切换块可操作以控制各个线圈段中的多个杆的连续性状态。

公开(公告)号：US20090168485A1

公开(公告)日：2009-07-02

申请号：US12398583

申请日：2009-03-05

申请人： Kyoung-Nam KIM ,  Ho-Youb Cho

发明人： Kyoung-Nam KIM ,  Ho-Youb Cho

IPC分类号： G11C19/00 ,  G11C7/00 ,  G11C8/18

CPC分类号： G11C19/28 ,  G11C7/1039 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096

摘要： A pipe latch device includes an output controller for outputting first and second output control signal groups based on a DLL clock signal and a driving signal; an input controller for generating an input control signal group; and a pipe latch unit for latching data on a data line when a corresponding input control signal is activated, and outputting latched data when a corresponding output control signal is activated, wherein the output controller includes a plurality of shifters, each for delaying an input data signal by half clock and one clock to output a first and second output signals in synchronization with the DLL clock signal and the driving signal; and a plurality of output control signal drivers for outputting the first and second output control signal groups based on the first and second output signals.

摘要翻译： 管闩锁装置包括：输出控制器，用于基于DLL时钟信号和驱动信号输出第一和第二输出控制信号组; 用于产生输入控制信号组的输入控制器; 以及管锁存单元，用于当相应的输入控制信号被激活时将数据锁存在数据线上，并且当相应的输出控制信号被激活时输出锁存的数据，其中输出控制器包括多个移位器，每个移位器用于延迟输入数据 信号通过半时钟和一个时钟与DLL时钟信号和驱动信号同步地输出第一和第二输出信号; 以及多个输出控制信号驱动器，用于基于第一和第二输出信号输出第一和第二输出控制信号组。

公开(公告)号：US07446579B2

公开(公告)日：2008-11-04

申请号：US11477530

申请日：2006-06-30

申请人： Kyoung-Nam Kim ,  Ho-Youb Cho

发明人： Kyoung-Nam Kim ,  Ho-Youb Cho

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G11C7/1072 ,  G11C7/222

摘要： A semiconductor memory device has a delay locked loop (DLL) with low power consumption. The semiconductor memory device includes a DLL for receiving an external clock to generate a DLL clock, an idle detector for detecting an idle state in which a command for driving a device is not supplied, and an output controller for controlling the output of the DLL through the idle state whether or not data is output.

摘要翻译： 半导体存储器件具有低功耗的延迟锁定环（DLL）。 半导体存储器件包括用于接收外部时钟以生成DLL时钟的DLL，用于检测未提供用于驱动器件的命令的空闲状态的空闲检测器，以及用于控制DLL的输出的输出控制器 空闲状态是否输出数据。

公开(公告)号：US07414446B2

公开(公告)日：2008-08-19

申请号：US11643916

申请日：2006-12-22

申请人： Kyoung Nam Kim

发明人： Kyoung Nam Kim

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  H03L7/091

摘要： A DLL circuit of a semiconductor memory apparatus includes a frequency sensing unit that generates and outputs a high frequency signal and a low frequency signal on the basis of a CAS latency signal. A clock dividing unit divides the frequency of an internal clock by a predetermined value and generates a divided clock in response with whether the high frequency signal is enabled or the low frequency signal is enabled. A phase sensing unit that switches a reference clock and a comparison clock, compares the phases thereof in accordance with whether the high frequency signal is enabled or the low frequency signal is enabled, selectively switches first and second phase control signals generated on the basis of the comparison result, and outputs the switched signals.

摘要翻译： 半导体存储装置的DLL电路包括频率感测单元，其基于CAS等待时间信号生成并输出高频信号和低频信号。 时钟分频单元将内部时钟的频率除以预定值，并且响应于高频信号是使能还是使能低频信号而产生分频时钟。 切换参考时钟和比较时钟的相位感测单元根据高频信号是使能还是使能低频信号进行比较，选择性地切换基于该时钟生成的第一和第二相位控制信号 比较结果，并输出开关信号。

公开(公告)号：US07394718B2

公开(公告)日：2008-07-01

申请号：US11789257

申请日：2007-04-24

申请人： Kyoung-Nam Kim ,  Seok-Cheol Yoon

发明人： Kyoung-Nam Kim ,  Seok-Cheol Yoon

IPC分类号： G11C8/00

CPC分类号： G11C5/063 ,  G11C8/10 ,  G11C11/4093

摘要： There is provided a semiconductor design technology, particularly, a bus line arrangement method of global data bus in the semiconductor memory device. According to the invention, skew by lines can be not occurred, or can be minimized upon an issuance thereof. Further, upon its issuance, it is easy to compensate it relying on the specific rule. The present invention proposes a scheme that classifies data transmission units corresponding to each bank into plural groups, each group having some continuous data transmission units, and makes bus lines of the global data bus to be arranged alternately for each group. In other words, the global data bus line arrangement scheme suggested by the present invention may be defined as grouped alternate arrangement scheme. In this case, the overlap interval between adjacent global data bus lines can be reduced largely and skew problem by lines can also be solved.

摘要翻译： 提供半导体设计技术，特别是半导体存储器件中的全局数据总线的总线布置方法。 根据本发明，可以不发生线偏斜，也可以在其发布时最小化。 此外，在发行时，很容易根据具体规则进行补偿。 本发明提出一种将每个存储体对应的数据传输单元分成多个组的方案，每个组具有一些连续的数据传输单元，并且使每个组交替布置全局数据总线的总线。 换句话说，本发明提出的全局数据总线布置方案可以被定义为分组的替代安排方案。 在这种情况下，相邻全局数据总线之间的重叠间隔可以大大减小，并且可以解决线上的倾斜问题。