公开(公告)号：US20070202641A1

公开(公告)日：2007-08-30

申请号：US11551263

申请日：2006-10-20

Applicant: Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

Inventor： Andy Wei ,  Thorsten Kammler ,  Jan Hoentschel ,  Manfred Horstmann

IPC: H01L21/337 ,  H01L21/22

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: By removing a portion of a halo region or by avoiding the formation of the halo region within the extension region, which may be subsequently formed on the basis of a re-grown semiconductor material, the threshold roll off behavior may be significantly improved, wherein an enhanced current drive capability may simultaneously be achieved.

Abstract translation: 通过去除晕圈区域的一部分或通过避免在延伸区域内形成卤区，其可以随后基于重新生长的半导体材料形成，可以显着改善阈值滚降行为，其中 可以同时实现增强的电流驱动能力。

公开(公告)号：US07217657B2

公开(公告)日：2007-05-15

申请号：US10260926

申请日：2002-09-30

Applicant: Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

Inventor： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

IPC: H01L21/44

CPC classification number: H01L29/665 ,  H01L21/28052 ,  H01L21/823418 ,  H01L21/823443 ,  H01L29/4933

Abstract: A method is disclosed in which differing metal layers are sequentially deposited on silicon-containing regions so that the type and thickness of the metal layers may be adapted to specific characteristics of the underlying silicon-containing regions. Subsequently, a heat treatment is performed to convert the metals into metal silicides so as to improve the electrical conductivity of the silicon-containing regions. In this way, silicide portions may be formed that are individually adapted to specific silicon-containing regions so that device performance of individual semiconductor elements or the overall performance of a plurality of semiconductor elements may be significantly improved. Moreover, a semiconductor device is disclosed comprising at least two silicon-containing regions having formed therein differing silicide portions, wherein at least one silicide portion comprises a noble metal.

Abstract translation: 公开了一种方法，其中不同的金属层依次沉积在含硅区域上，使得金属层的类型和厚度可以适应于下面的含硅区域的特定特性。 随后，进行热处理以将金属转化为金属硅化物，从而提高含硅区域的导电性。 以这种方式，可以形成独立地适应特定的含硅区域的硅化物部分，从而可以显着改善各个半导体元件的器件性能或多个半导体元件的整体性能。 此外，公开了一种半导体器件，其包括至少两个其中形成有不同硅化物部分的含硅区域，其中至少一个硅化物部分包括贵金属。

公开(公告)号：US20070096148A1

公开(公告)日：2007-05-03

申请号：US11466572

申请日：2006-08-23

Applicant: Jan Hoentschel ,  Andy Wei ,  Manfred Horstmann ,  Thorsten Kammler

Inventor： Jan Hoentschel ,  Andy Wei ,  Manfred Horstmann ,  Thorsten Kammler

IPC: H01L31/00

CPC classification number: H01L29/78684 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: By forming a deep recess through the buried insulating layer and re-growing a strained semiconductor material, an enhanced strain generation mechanism may be provided in SOI-like transistors. Consequently, the strain may also be efficiently created by the embedded strained semiconductor material across the entire active layer, thereby significantly enhancing the performance of transistor devices, in which two channel regions may be defined.

Abstract translation: 通过形成通过掩埋绝缘层的深凹槽并重新生长应变半导体材料，可以在SOI类晶体管中提供增强的应变产生机制。 因此，也可以通过整个有源层上的嵌入的应变半导体材料有效地产生应变，从而显着提高可以限定两个沟道区的晶体管器件的性能。

公开(公告)号：US07060549B1

公开(公告)日：2006-06-13

申请号：US11174400

申请日：2005-07-01

Applicant: Mark Craig ,  Karsten Wieczorek ,  Manfred Horstmann

Inventor： Mark Craig ,  Karsten Wieczorek ,  Manfred Horstmann

IPC: H01L21/8238

CPC classification number: H01L29/7843 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/78

Abstract: SRAM devices utilizing tensile-stressed strain films and methods for fabricating such SRAM devices are provided. An SRAM device, in one embodiment, comprises an NFET and a PFET that are electrically coupled and physically isolated. The PFET has a gate region, a source region, and a drain region. A tensile-strained stress film is disposed on the gate region and at least a portion of the source region and the drain region of the PFET. A method for fabricating a cell of an SRAM device comprises fabricating an NFET and a PFET overlying a substrate. The PFET and the NFET are electically coupled and are physically isolated. A tensile-strained stress film is deposited on the gate region and at least a portion of the source region and the drain region of the PFET.

Abstract translation: 提供了使用拉伸应力应变膜的SRAM器件和制造这种SRAM器件的方法。 在一个实施例中，SRAM器件包括电耦合和物理隔离的NFET和PFET。 PFET具有栅极区域，源极区域和漏极区域。 拉伸应变应力膜设置在栅极区域和PFET的源极区域和漏极区域的至少一部分上。 用于制造SRAM器件的单元的方法包括制造覆盖衬底的NFET和PFET。 PFET和NFET电耦合并且物理隔离。 在栅极区域和PFET的源极区域和漏极区域的至少一部分上沉积拉伸应变膜。

公开(公告)号：US20060046400A1

公开(公告)日：2006-03-02

申请号：US11114262

申请日：2005-04-26

Applicant: Gert Burbach ,  Rolf Stephan ,  Karsten Wieczorek ,  Manfred Horstmann

Inventor： Gert Burbach ,  Rolf Stephan ,  Karsten Wieczorek ,  Manfred Horstmann

IPC: H01L21/336

CPC classification number: H01L29/7842 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/7843

Abstract: A semiconductor structure comprising a first transistor element and a second transistor element is provided. Stress in channel regions of the first and the second transistor element is controlled by forming stressed layers having a predetermined stress over the transistors. The stressed layers may be used as etch stop layers in the formation of contact vias through an interlayer dielectric formed over the transistors.

Abstract translation: 提供包括第一晶体管元件和第二晶体管元件的半导体结构。 通过在晶体管上形成具有预定应力的应力层来控制第一和第二晶体管元件的沟道区域中的应力。 应力层可以用作通过在晶体管上形成的层间电介质形成接触孔的蚀刻停止层。

公开(公告)号：US20060043430A1

公开(公告)日：2006-03-02

申请号：US11122740

申请日：2005-05-05

Applicant: Thomas Feudel ,  Manfred Horstmann ,  Markus Lenski

Inventor： Thomas Feudel ,  Manfred Horstmann ,  Markus Lenski

IPC: H01L29/76

CPC classification number: H01L21/823814 ,  H01L21/26586 ,  H01L21/823807 ,  H01L29/66659 ,  H01L29/7835

Abstract: By providing an asymmetric design of a halo region and extension regions of a field effect transistor, the transistor performance may significantly be enhanced for a given basic transistor architecture. In particular, a large overlap area may be created at the source side with a steep concentration gradient of the PN junction due to the provision of the halo region, whereas the drain overlap may be significantly reduced or may even completely be avoided, wherein a moderately reduced concentration gradient may further enhance the transistor performance.

Abstract translation: 通过提供场效应晶体管的光晕区域和延伸区域的非对称设计，对于给定的基本晶体管架构，晶体管性能可以显着增强。 特别地，由于提供了卤素区域，可能在源极侧产生具有PN结的陡峭浓度梯度的大的重叠区域，而可以显着地减少或甚至可以完全避免漏极重叠，其中适度地 降低的浓度梯度可进一步提高晶体管的性能。

公开(公告)号：US06924216B2

公开(公告)日：2005-08-02

申请号：US10440640

申请日：2003-05-19

Applicant: Thomas Feudel ,  Manfred Horstmann ,  Rolf Stephan

Inventor： Thomas Feudel ,  Manfred Horstmann ,  Rolf Stephan

IPC: H01L21/265 ,  H01L21/425

CPC classification number: H01L21/26586 ,  H01L21/26506 ,  H01L21/26513

Abstract: A method of forming the active regions of field effect transistors is proposed. According to the proposed method, shallow implanting profiles for both the halo structures and the source and drain regions can be obtained by carrying out a two-step damaging and amorphizing implantation process. During a first step, the substrate is damaged during a first light ion implantation step and subsequently substantially fully amorphized during a second heavy ion implantation step.

Abstract translation: 提出了一种形成场效应晶体管有源区的方法。 根据所提出的方法，可以通过进行两步损伤和非晶化注入工艺来获得卤素结构和源极和漏极区域的浅注入分布。 在第一步骤期间，衬底在第一轻离子注入步骤期间损坏，并且随后在第二重离子注入步骤期间基本上完全非晶化。

公开(公告)号：US06754553B2

公开(公告)日：2004-06-22

申请号：US09820033

申请日：2001-03-28

Applicant: Karsten Wieczorek ,  Manfred Horstmann ,  Christian Krueger

Inventor： Karsten Wieczorek ,  Manfred Horstmann ,  Christian Krueger

IPC: G06F1900

CPC classification number: H01L22/10 ,  H01J2237/30433 ,  H01J2237/31701 ,  H01L21/26506 ,  H01L21/2658

Abstract: Test wafer consumption is a significant contributor to overall cost of manufacturing in semiconductor industry due to scrapping the test wafers after one monitoring of implantation parameters. This invention provides a method to reuse the same test wafer for monitoring the implantation parameters more than once. This method comprises the possibility of implanting the same implant species together with identical implanting and annealing conditions as well as of implanting a broad variety of implant species together with varying implanting and annealing conditions. Therefore, this invention helps to significantly reduce the number of test wafers consumed in the implant-area.

Abstract translation: 测试晶片消耗是半导体工业制造总体成本的重要因素，因为在一次监测植入参数之后报废测试晶片。 本发明提供一种重复使用相同测试晶片多于一次来监测注入参数的方法。 该方法包括以相同的植入和退火条件以及植入各种植入物种以及不同的植入和退火条件一起植入相同植入物种的可能性。 因此，本发明有助于显着减少在植入区域中消耗的测试晶片的数量。

公开(公告)号：US06673665B2

公开(公告)日：2004-01-06

申请号：US10210637

申请日：2002-07-31

Applicant: Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

Inventor： Karsten Wieczorek ,  Manfred Horstmann ,  Rolf Stephan

IPC: H01L218234

CPC classification number: H01L29/66507 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665

Abstract: The surface area of silicon lines which receives a silicide portion is increased to decrease the line resistance in narrow polysilicon lines, such as gate electrodes. Sidewall spacers are formed such that an upper portion of the line sidewall is exposed so as to react with a refractory metal to form a low resistance silicide. The upper portion may be exposed by overetching the dielectric layer deposited to form the sidewall spacers.

Abstract translation: 接收硅化物部分的硅线的表面积增加，以减小诸如栅电极的窄多晶硅线中的线电阻。 侧壁间隔件形成为使得侧壁的上部被暴露以与难熔金属反应以形成低电阻硅化物。 可以通过过蚀刻沉积以形成侧壁间隔物的介电层来暴露上部。

公开(公告)号：US06281086B1

公开(公告)日：2001-08-28

申请号：US09422548

申请日：1999-10-21

Applicant: Karsten Wieczorek ,  Manfred Horstmann ,  Tilo Mantei

Inventor： Karsten Wieczorek ,  Manfred Horstmann ,  Tilo Mantei

IPC: H01L21336

CPC classification number: H01L29/66507 ,  H01L21/28052 ,  H01L21/28105 ,  H01L29/4966

Abstract: A semiconductor device and a method of fabricating the same is provided, wherein the semiconductor device exhibits a lower gate delay time when compared to that of a conventional semiconductor device. The reduction of gate delay time is achieved by providing a conductive layer enclosing the gate electrode so as to significantly increase the surface portion of the gate electrode having a low electric resistance. For example, providing a substantially inverted U-shaped silicide layer enclosing the gate electrode leads to a decrease in the electrical resistance of about 67% with a given aspect ratio of about 1. Moreover, reducing the gate length, i.e., increasing the aspect ratio of the gate electrode results in a nearly complete independence of the gate resistance from the gate length.

Abstract translation: 提供一种半导体器件及其制造方法，其中与常规半导体器件相比，半导体器件表现出较低的栅极延迟时间。 栅极延迟时间的减小通过提供包围栅电极的导电层来显着增加具有低电阻的栅电极的表面部分来实现。 例如，提供围绕栅电极的大致倒U形硅化物层导致电阻降低约67％，给定的纵横比约为1.此外，减小栅极长度，即增加纵横比 的栅电极导致栅极电阻几乎完全独立于栅极长度。