公开(公告)号：US20060067146A1

公开(公告)日：2006-03-30

申请号：US10954941

申请日：2004-09-30

Applicant: Steven Woo ,  Michael Ching ,  Chad Bellows ,  Wayne Richardson ,  Kurt Knorpp ,  Jun Kim

Inventor： Steven Woo ,  Michael Ching ,  Chad Bellows ,  Wayne Richardson ,  Kurt Knorpp ,  Jun Kim

IPC: G11C7/02

CPC classification number: G11C7/106 ,  G11C7/065 ,  G11C7/1045 ,  G11C7/1051

Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in dynamic memory bank count and page size mode. The integrated circuit memory device includes a first and second row of storage cells coupled to a row of sense amplifiers including a first and second plurality of sense amplifiers. During the first mode of operation, a first plurality of data is transferred from the first plurality of storage cells to the row of sense amplifiers. During the second mode of operation, a second plurality of data is transferred from the first row of storage cells to the first plurality of sense amplifiers and a third plurality of data is transferred from the second row of storage cells to the second plurality of sense amplifiers. The second and third plurality of data is accessible simultaneously from the memory device interface during the second mode of operation. In an embodiment, the second plurality of data is transferred from the first half of the first row and the third plurality of data is transferred from the second half of the second row.

Abstract translation: 存储器系统包括主设备，诸如图形控制器或处理器，以及可以动态存储器库计数和页大小模式操作的集成电路存储器件。 集成电路存储器件包括耦合到包括第一和第二多个读出放大器的读出放大器行的第一和第二行存储单元。 在第一操作模式期间，第一多个数据从第一多个存储单元传送到读出放大器行。 在第二操作模式期间，第二多个数据从第一行存储单元转移到第一多个读出放大器，并且第三多个数据从第二行存储单元传送到第二多个读出放大器 。 在第二操作模式期间，第二和第三多个数据可以从存储器设备接口同时访问。 在一个实施例中，第二多个数据从第一行的前半部分传送，第三个数据从第二行的后半部分传送。

公开(公告)号：US20060022724A1

公开(公告)日：2006-02-02

申请号：US11237276

申请日：2005-09-27

Applicant: Jared Zerbe ,  Michael Ching ,  Abhijit Abhyankar ,  Richard Barth ,  Andy Chan ,  Paul Davis ,  William Stonecypher

Inventor： Jared Zerbe ,  Michael Ching ,  Abhijit Abhyankar ,  Richard Barth ,  Andy Chan ,  Paul Davis ,  William Stonecypher

IPC: H03L7/00

CPC classification number: G06F1/12 ,  G06F13/423 ,  H03L7/085 ,  H04L7/0012 ,  H04L7/0045 ,  H04L7/0054 ,  H04L7/02 ,  H04L7/0337

Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.