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72 条记录 (耗时 0.018 秒)

    Flow control, latency control, and bitrate conversions in a timing correction and frame synchronization apparatus
    41.
    发明授权
    Flow control, latency control, and bitrate conversions in a timing correction and frame synchronization apparatus 有权
    时序校正和帧同步装置中的流控制，等待时间控制和比特率转换

    公开(公告)号：US06330286B1

    公开(公告)日：2001-12-11

    申请号：US09589775

    申请日：2000-06-08

    申请人： Paul Wallace Lyons ,  John Prickett Beltz ,  Alfonse Anthony Acampora

    发明人： Paul Wallace Lyons ,  John Prickett Beltz ,  Alfonse Anthony Acampora

    IPC分类号： H04N712

    CPC分类号： H04N21/23424 ,  H04N21/23406 ,  H04N21/23608 ,  H04N21/44004 ,  H04N21/44016

    摘要： In a compressed domain digital communications system, a method for reducing a variable latency associated with a buffer and at least partially resulting from at least one splice between a FROM bitstream and a TO bitstream each including data corresponding to a plurality of frames, the method including: selectively deleting data corresponding to a select at least one of the frames from the buffer based upon the variable latency so as to reduce the variable latency when an amount of data corresponding to a number of frames present in the buffer is greater than a given number of frames; and, regulating a flow of data in the system to prevent an underflow condition in the system by effecting a repeat last frame command and prevent an overflow condition in the system by slowing a rate of transmission for the data associated with at least one of the frames in the TO bitstream.

    摘要翻译： 在压缩域数字通信系统中，一种减少与缓冲器相关联的可变延迟并且至少部分地由FROM位流和TO位流之间的至少一个拼接产生的方法，每一个包含对应于多个帧的数据，该方法包括 基于所述可变延迟，有选择地从所述缓冲器中删除与所述缓冲器中的至少一个选择对应的数据，以便当与所述缓冲器中存在的帧的数量相对应的数据量大于给定数量时，减少所述可变等待时间 的框架 并且通过执行重复的最后帧命令来调节系统中的数据流以防止系统中的下溢状况，并通过减慢与至少一个帧相关联的数据的传输速率来防止系统中的溢出状况 在TO比特流中。

    Methods for detecting cancer cells by using humanized antibodies which bind specifically to FB5 antigen
    42.
    发明授权
    Methods for detecting cancer cells by using humanized antibodies which bind specifically to FB5 antigen 有权
    通过使用特异性结合FB5抗原的人源化抗体检测癌细胞的方法

    公开(公告)号：US06217868B1

    公开(公告)日：2001-04-17

    申请号：US09184198

    申请日：1998-11-02

    申请人： Thomas Paul Wallace ,  Francis Carr ,  Wolfgang J. Rettig ,  Pilar Garin-Chesa ,  Lloyd J. Old

    发明人： Thomas Paul Wallace ,  Francis Carr ,  Wolfgang J. Rettig ,  Pilar Garin-Chesa ,  Lloyd J. Old

    IPC分类号： A61K39395

    CPC分类号： C07K16/30 ,  C07K2317/24 ,  C07K2319/00

    摘要： The invention provides for the production of several humanized murine antibodies specific for the antigen FB5, which is recognized by the murine antibody FB5. The FB5 antigen is expressed on the luminal surface of vascular endothelial cells of a wide range of malignant tumors. The invention also provides for numerous polynucleotide encoding humanized FB5 specific antibodies, expression vectors for producing humanized FB5 specific antibodies, and host cells for the recombinant production of the humanized antibodies. The invention also provides methods for detecting cancerous cells (in vitro and in vivo) using humanized FB5 specific antibodies. Additionally, the invention provides methods of treating cancer using FB5 specific antibodies.

    摘要翻译： 本发明提供了针对抗原FB5特异的几种人源化鼠抗体的产生，其被鼠抗体FB5识别。 FB5抗原在广泛恶性肿瘤的血管内皮细胞的腔表面上表达。 本发明还提供编码人源化FB5特异性抗体的许多多核苷酸，用于产生人源化FB5特异性抗体的表达载体和用于重组产生人源化抗体的宿主细胞。 本发明还提供使用人源化FB5特异性抗体检测癌细胞（体外和体内）的方法。 另外，本发明提供了使用FB5特异性抗体治疗癌症的方法。

    Method and apparatus for storing data in a sequentially written memory using an interleaving mechanism
    44.
    发明授权
    Method and apparatus for storing data in a sequentially written memory using an interleaving mechanism 失效
    使用交织机构将数据存储在顺序写入的存储器中的方法和装置

    公开(公告)号：US06026473A

    公开(公告)日：2000-02-15

    申请号：US771847

    申请日：1996-12-23

    申请人： Leonard W. Cross ,  Edward Paul Wallace

    发明人： Leonard W. Cross ,  Edward Paul Wallace

    IPC分类号： G06F5/16 ,  G06F13/16 ,  G06F12/00 ,  G06F13/00

    CPC分类号： G06F5/16 ,  G06F13/1647

    摘要： A method and apparatus for storing data values received within respective cycle periods of a clock signal are disclosed. Data values are alternately stored in first and second data hold registers and then output by each data hold register for a time greater than a cycle period of the clock signal. Address values at which the incoming data values are to be written are alternately stored in first and second address hold registers. Data stored in the first data hold register is written to a latch-based memory element in a first memory bank indicated by an address value stored in the first address hold register. Data stored in the second data hold register is written to a latch-based memory element in a second memory bank indicated by an address value stored in the second address hold register.

    摘要翻译： 公开了一种用于存储在时钟信号的各个周期周期内接收的数据值的方法和装置。 数据值交替存储在第一和第二数据保持寄存器中，然后由每个数据保持寄存器输出大于时钟信号周期的时间。 输入数据值要被写入的地址值交替存储在第一和第二地址保持寄存器中。 存储在第一数据保持寄存器中的数据被写入由存储在第一地址保持寄存器中的地址值指示的第一存储体中的基于锁存器的存储元件。 存储在第二数据保持寄存器中的数据被写入由存储在第二地址保持寄存器中的地址值指示的第二存储体中的基于锁存器的存储元件。

    Method and apparatus for opportunistically transferring data in a packet stream encoder
    45.
    发明授权
    Method and apparatus for opportunistically transferring data in a packet stream encoder 失效
    用于机会地传送分组流编码器中的数据的方法和装置

    公开(公告)号：US5864557A

    公开(公告)日：1999-01-26

    申请号：US719807

    申请日：1996-09-25

    申请人： Paul Wallace Lyons

    发明人： Paul Wallace Lyons

    IPC分类号： H04J3/00 ,  H04J3/16 ,  H04J3/24 ,  H04N21/236 ,  H04N21/2365 ,  H04N21/434

    CPC分类号： H04N21/4347 ,  H04J3/247 ,  H04N21/236 ,  H04N21/2365 ,  H04N21/434

    摘要： A transport stream encoder comprises a plurality of component signal sources. One of the component signals sources is a source of an opportunistic data component signal carrying a block of data having a predetermined size to be transferred within a predetermined period of time. A packet generator is coupled to the plurality of component signal sources, and produces a composite packet stream, partitioned into successive groups containing a plurality of packet slots. A memory stores a plurality of priority lists respectively associated with the plurality of packet slots. Each priority list contains a plurality of entries, and each entry contains data representing a respective one of the plurality of component signal sources. A scheduler is responsive to the entries in the plurality of priority lists and conditions the packet generator to generate a packet for each one of the packet slots. The generated packet contains data from a component signal source selected from among the component signal sources having representative data in the entries in the priority list associated with that packet slot. A processor modifies the entries in the plurality of priority lists in such a manner as to ensure that a packet containing data from the opportunistic data component signal source is generated with sufficient time regularity to guarantee that the block of data is transferred within the predetermined time period.

    摘要翻译： 传输流编码器包括多个分量信号源。 分量信号源中的一个是在预定时间段内传送具有预定尺寸的数据块的机会数据分量信号的源。 分组生成器耦合到多个分量信号源，并产生分组成包含多个分组时隙的连续组的复合分组流。 存储器存储分别与多个分组时隙相关联的多个优先级列表。 每个优先级列表包含多个条目，并且每个条目包含表示多个分量信号源中的相应一个的数据。 调度器响应多个优先级列表中的条目，并且使分组生成器为每个分组时隙生成分组。 所生成的分组包含来自在与该分组时隙相关联的优先级列表中的条目中具有代表性数据的分量信号源中选择的分量信号源的数据。 处理器以这样的方式修改多个优先级列表中的条目，以便确保以足够的时间规则生成包含来自机会数据分量信号源的数据的分组，以保证数据块在预定时间段内被传送 。

    Load indicating member, apparatus and method
    46.
    发明授权
    Load indicating member, apparatus and method 失效

    公开(公告)号：US4676109A

    公开(公告)日：1987-06-30

    申请号：US670260

    申请日：1984-11-13

    申请人： Paul Wallace

    发明人： Paul Wallace

    IPC分类号： G01L5/00 ,  B25B23/14 ,  B25B23/147 ,  F16B31/02 ,  G01L5/24 ,  G01L1/04

    CPC分类号： B25B23/147 ,  B25B23/14 ,  F16B31/025 ,  G01L5/24

    摘要： A method of measuring the load in a member subjected to longitudinal stress, a load measuring device and a fastener tightening device using the method of measuring, a load indicating member and a load indicating fastener for use in conjunction with the method of measuring, a method of making the load indicating fastener, and a method of tightening the load indicating fastener. A preselected end of a pin is secured to a shank of a load indicating member, such as a load indicating fastener, in a manner such that the pin is unaffected by the elastic deformation of the shank in response to longitudinal stress. Coplanar first and second flat surfaces are formed, respectively, adjacent to the longitudinal ends of the pin and the shank furthest from the preselected end of the pin such as to provide reference surfaces for the measurement of the elongation of the shank in response to longitudinal stress.

    SIMD addition circuit
    48.
    发明授权
    SIMD addition circuit 有权
    SIMD加法电路

    公开(公告)号：US07219118B2

    公开(公告)日：2007-05-15

    申请号：US10283246

    申请日：2002-10-30

    申请人： Andrew Paul Wallace

    发明人： Andrew Paul Wallace

    IPC分类号： G06F7/38 ,  G06F7/50

    CPC分类号： G06F7/505 ,  G06F7/508 ,  G06F2207/382 ,  G06F2207/3828

    摘要： A system for adding multiple sets of numbers via a fixed-width adder includes an adder for receiving each of the sets of binary numbers at corresponding sets of adder inputs, and for generating a sum of each set of binary numbers. Each set of numbers defines a distinct data path through the adder. For each set of numbers, the system further includes a logic gate for inhibiting a carry path, from each portion of the adder corresponding to each carry path, to a next adjacent carry path. The system isolates two or more contiguous data paths through the fixed-width adder corresponding to each of the two or more sets of two binary numbers. The invention prevents unwanted signals from crossing summing lane boundaries in different processing modes. The same adder logic can thus be used for each processing mode by varying the combination of mode select control signals.

    摘要翻译： 一种通过固定宽度加法器添加多组数字的系统包括一个加法器，用于接收相应的加法器输入集合中的每一组二进制数，并产生每组二进制数的和。 每组数字通过加法器定义不同的数据路径。 对于每组数字，系统还包括用于禁止从每个进位路径对应的加法器的每个部分到下一个相邻进位路径的进位路径的逻辑门。 系统通过固定宽度加法器隔离两个或更多个连续数据路径，对应于两组或两组二进制数中的每一个。 本发明可防止不同信号在不同处理模式下通过相加车道边界。 因此，通过改变模式选择控制信号的组合，相同的加法器逻辑可以用于每个处理模式。

    Oligomer and polymer comprising triphenyl phosphine units
    50.
    发明申请
    Oligomer and polymer comprising triphenyl phosphine units 有权
    含有三苯基膦单元的低聚物和聚合物

    公开(公告)号：US20070031698A1

    公开(公告)日：2007-02-08

    申请号：US10568659

    申请日：2004-08-18

    申请人： Carl Towns ,  Ian Rees ,  Ilaria Grizzi ,  Paul Wallace

    发明人： Carl Towns ,  Ian Rees ,  Ilaria Grizzi ,  Paul Wallace

    IPC分类号： B32B19/00

    CPC分类号： H01L51/0036 ,  C08G61/12 ,  C09K11/06 ,  C09K2211/1433 ,  H01L51/0035 ,  H01L51/0043 ,  H01L51/0059 ,  H05B33/14

    摘要： An oligomer or polymer comprising a first repeat unit and a second repeat unit that may be the same or different, the first repeat unit having formula (I): wherein each E independently represents optionally substituted nitrogen or optionally substituted phosphorus, with the proviso that at least one E is optionally substituted phosphorus; each Ar1, Ar2 and Ar3 is the same or different and independently represents an optionally substituted aryl or heteroaryl; n is 0-3; and in the case of unsubstituted nitrogen and phosphorus, the second repeat unit is directly conjugated to the first repeat unit.

    摘要翻译： 包含可以相同或不同的第一重复单元和第二重复单元的低聚物或聚合物具有式（I）的第一重复单元：其中每个E独立地表示任选取代的氮或任选取代的磷，条件是在 至少一个E是任选取代的磷; 每个Ar 1，Ar 2和Ar 3相同或不同，并且独立地表示任选取代的芳基或杂芳基; n为0-3; 在未被取代的氮和磷的情况下，第二重复单元直接与第一重复单元结合。