公开(公告)号：US20220216096A1

公开(公告)日：2022-07-07

申请号：US17160402

申请日：2021-01-28

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Yen-Jhih Huang

IPC分类号： H01L21/768 ,  H01L21/321 ,  H01L21/3213

摘要： A planarization method including the following steps is provided. A substrate is provided. The substrate includes a first region and a second region. A material layer is formed on the substrate. The top surface of the material layer in the first region is lower than the top surface of the material layer in the second region. A patterned photoresist layer is formed on the material layer in the first region. A first etching process is performed on the patterned photoresist layer, so that the top surface of the patterned photoresist layer and the top surface of the material layer in the second region have substantially the same height. A second etching process is performed on the patterned photoresist layer and the material layer. In the second etching process, the etching rate of the patterned photoresist layer is substantially the same as the etching rate of the material layer.

公开(公告)号：US20220155673A1

公开(公告)日：2022-05-19

申请号：US17120278

申请日：2020-12-14

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Yi-Kai Lai

IPC分类号： G03F1/26 ,  G03F7/20 ,  H01L21/027

摘要： A phase shift mask suitable for forming a via pattern on a transferred object is provided. The phase shift mask has a first pattern region and a second pattern region. The phase shift mask includes a substrate and a phase shift pattern layer. The phase shift pattern layer is located on the substrate and is disposed corresponding to one of the first pattern region and the second pattern region. An optical phase difference corresponding to the first pattern region and the second pattern region is basically 180 degrees. The first pattern region has a via region away from the second pattern region. The second pattern region includes a plurality of strip patterns surrounding the via region.

公开(公告)号：US11329056B2

公开(公告)日：2022-05-10

申请号：US16931411

申请日：2020-07-16

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shou-Zen Chang ,  Yi-Hsung Wei ,  Jia-You Lin ,  Pei-Hsiu Tseng ,  Chih-Peng Lee ,  Chi-Wei Lin

IPC分类号： H01L27/11 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/768 ,  H01L49/02

摘要： A SRAM device includes a substrate, at least one two-transistor static random access memory (2T-SRAM), an inner dielectric layer, a plurality of contacts, an inter-layer dielectric (ILD) layer, a plurality of vias, and a conductive line. The 2T-SRAM is disposed on the substrate, the inner dielectric layer covers the 2T-SRAM, and the contacts are disposed in the inner dielectric layer and coupled to the 2T-SRAM. The ILD layer covers the inner dielectric layer and the contacts, and the vias are disposed in the ILD layer and respectively coupled to the 2T-SRAM trough the corresponding contacts. The conductive line is disposed on the ILD layer and connects with the plurality of vias, wherein the thickness of the conductive line is less than or equal to one-tenth of the thickness of the via such that it can significantly reduce the coupling effect compared with the traditional bit line.

公开(公告)号：US20220108993A1

公开(公告)日：2022-04-07

申请号：US16952078

申请日：2020-11-19

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Zih-Song Wang

IPC分类号： H01L27/1157 ,  H01L27/11582 ,  H01L29/78

摘要： A 3D NAND flash memory device includes a substrate, a source line on the substrate, a stacked structure on the source line, a bit line on the stacked structure, and a columnar channel portion. The stacked structure includes a first select transistor, memory cells, and a second select transistor, wherein the first select transistor includes a first select gate, the memory cells include control gates, and the second select transistor includes a second select gate. The columnar channel portion is extended axially from the source line and penetrates the stacked structure to be coupled to the bit line. The first select transistor includes a modified Schottky barrier (MSB) transistor to generate direct tunneling of majority carriers to the columnar channel portion to perform a program operation or an erase operation.

公开(公告)号：US11289470B2

公开(公告)日：2022-03-29

申请号：US17115799

申请日：2020-12-09

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Wei-Yu Lin ,  Shih-Hao Cheng

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L27/02 ,  H01L21/04 ,  H01L21/324 ,  H01L21/761

摘要： A method of manufacturing a trench transistor structure including the following steps is provided. A substrate structure is provided. A first region and a second region are defined in the substrate structure. The substrate structure has a first trench located in the first region and a second trench located in the second region. A transistor device is formed in the first region. The transistor device includes an electrode located in the first trench. The electrode and the substrate structure are isolated from each other. An electrostatic discharge (ESD) protection device is formed in the second region. The ESD protection device includes a main body layer located in the second trench. The main body layer has a planarized top surface. PN junctions are located in the main body layer. The main body layer and the substrate structure are isolated from each other.

公开(公告)号：US11257830B2

公开(公告)日：2022-02-22

申请号：US17115811

申请日：2020-12-09

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Wen-Yueh Jang

IPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/788 ,  H01L27/11558 ,  H01L27/11519

摘要： In the memory structure, a pair of gate stack structures is on a first dielectric layer and separated from each other. Each of the gate stack structures includes a word line and a second dielectric layer. A third dielectric layer is on the sidewall of the gate stack structures. A pair of floating gates is between the gate stack structures. Each of the floating gates is on the third dielectric layer on the sidewall of the corresponding gate stack structure. The top surface of the floating gates is not higher than the that of the second dielectric layer. A fourth dielectric layer covers the first and third dielectric layers, and the floating gates. A control gate is on the fourth dielectric layer between the floating gates. A doped region is in the substrate beside the gate stack structures. An erase gate is above the control gate and the floating gates.

公开(公告)号：US20220037503A1

公开(公告)日：2022-02-03

申请号：US17019328

申请日：2020-09-13

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Wen Chung Yang ,  Shih Hsi Chen ,  Wei-Chang Lin

IPC分类号： H01L29/49 ,  H01L29/423 ,  H01L29/788 ,  H01L21/02 ,  H01L21/311 ,  H01L21/764 ,  H01L21/28 ,  H01L29/66

摘要： Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.

公开(公告)号：US20210391451A1

公开(公告)日：2021-12-16

申请号：US17000371

申请日：2020-08-24

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Chun-Sheng Chen ,  Yen-Cheng Fang ,  Zih-Han Chen

IPC分类号： H01L29/739 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66

摘要： An insulated gate bipolar transistor (IGBT) structure including a substrate and a first gated PNPN diode is provided. The first gated PNPN diode is located on the substrate. The first gated PNPN diode includes a first gate, a first source/drain extension (SDE) region, and a second SDE region. The first gate is located on the substrate. The first SDE region and the second SDE region are located in the substrate on two sides of the first gate.

公开(公告)号：US20210351267A1

公开(公告)日：2021-11-11

申请号：US16905926

申请日：2020-06-19

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Chun-Sheng Chen

IPC分类号： H01L49/02 ,  H01G4/30 ,  G06F30/10

摘要： A multilayer capacitive element and a design method of the same are provided. The capacitive element includes a substrate having a groove, a first aspect ratio modulation structure, and a plurality of conductive layers and a plurality of dielectric layers. The first aspect ratio modulation structure is located in the groove to define the groove as a first region and a first modulation region, wherein an aspect ratio of the first modulation region is different from that of the first region. The plurality of conductive layers and the plurality of dielectric layers are alternately stacked in the groove.

公开(公告)号：US20210351179A1

公开(公告)日：2021-11-11

申请号：US16925308

申请日：2020-07-09

申请人： Powerchip Semiconductor Manufacturing Corporation

发明人： Shih-Chieh Pu ,  Jih-Wen Chou ,  Chih-Chung Tai

IPC分类号： H01L27/088 ,  H01L21/8234

摘要： An integrated circuit including a substrate, a first semiconductor element, and a second semiconductor element is provided. The substrate has a high voltage region and a low voltage region separated from each other. The first semiconductor element is located in the high voltage region. The first semiconductor element includes a first oxide layer and a first gate. The first oxide layer is embedded in the substrate. The first gate is located on the first oxide layer. The first gate is a polycrystalline gate. The second semiconductor element is located in the low voltage region. The second semiconductor element includes a second oxide layer and a second gate. The second oxide layer is embedded in the substrate. The second gate is located on the second oxide layer. The second gate is a metal gate. A manufacturing method of an integrated circuit is also provided.