公开(公告)号：US20120271001A1

公开(公告)日：2012-10-25

申请号：US13174017

申请日：2011-06-30

申请人： Choon Soo Lee ,  Min Hee Lee ,  Bong Hyun Park ,  Seong Hoon Lee ,  Jong Hwal Kim ,  Sung Kyoun Yoon ,  Byoung Gook Kang

发明人： Choon Soo Lee ,  Min Hee Lee ,  Bong Hyun Park ,  Seong Hoon Lee ,  Jong Hwal Kim ,  Sung Kyoun Yoon ,  Byoung Gook Kang

IPC分类号： C08L61/02 ,  C08L43/00 ,  C08L33/14 ,  C08L51/06 ,  C08L77/06

CPC分类号： C08L61/02 ,  C08L23/16 ,  C08L51/04 ,  C08L77/02 ,  C08L77/06 ,  C08L33/12

摘要： The present invention provides a polyketone composition having about 40˜90 wt % of polyketone, about 5˜40 wt % of polyamide, and about 5˜20 wt % of modified rubber. The composition of the present invention greatly improves the impact resistance of polyketone, which has increased heat resistance, chemical resistance, fuel permeation resistance, abrasion resistance or the like, and thus may be widely applied in various industrial fields, such as automotive parts including wheel covers, wheel caps, fuel filler necks, fuel tanks, fuel tubes, center fascias, door handles, roof rack covers, gear, junction boxes, connectors, seat backs or the like, electric/electronic parts, and household items, thereby providing durability of the parts and price competition.

摘要翻译： 本发明提供了具有约40〜90重量％聚酮，约5〜40重量％聚酰胺和约5〜20重量％改性橡胶的聚酮组合物。 本发明的组合物大大提高了耐热性，耐化学药品性，耐燃油渗透性，耐磨耗性等的聚酮的耐冲击性，因此可广泛应用于各种工业领域，例如包括车轮 盖子，轮盖，燃油加注口，燃料箱，燃料管，中心筋，门把手，车顶架盖，齿轮，接线盒，连接器，座椅靠背等，电气/电子零件和家居用品，从而提供耐久性 的零件和价格竞争。

公开(公告)号：US08289796B2

公开(公告)日：2012-10-16

申请号：US12694136

申请日：2010-01-26

申请人： Seong-Hoon Lee

发明人： Seong-Hoon Lee

IPC分类号： G11C7/02

CPC分类号： G11C7/065 ,  G11C7/062 ,  G11C7/08 ,  G11C7/12 ,  H03F3/45179 ,  H03G3/00

摘要： Memories, sense amplifiers, and methods for amplifying a current input are disclosed, including a sense amplifier including a bias circuit configured to provide a bias voltage having a magnitude responsive to maintaining a substantially constant loop gain, and further including an amplifier stage coupled to the bias circuit to receive the bias voltage and configured to amplify a input current at an input-output node, a loop gain of the current amplifier stage is controlled at least in part to the bias voltage.

摘要翻译： 公开了用于放大电流输入的存储器，感测放大器和放大电流输入的方法，包括读出放大器，其包括偏置电路，该偏置电路被配置为提供具有响应于保持基本上恒定的环路增益的幅度的偏置电压，并且还包括耦合到 偏置电路以接收所述偏置电压并且被配置为放大输入 - 输出节点处的输入电流，所述电流放大器级的环路增益至少部分地被控制为所述偏置电压。

公开(公告)号：US08134391B2

公开(公告)日：2012-03-13

申请号：US12581435

申请日：2009-10-19

申请人： Seong-hoon Lee

发明人： Seong-hoon Lee

IPC分类号： H03L7/00 ,  G06F1/12

CPC分类号： H03L7/07 ,  G06F1/10 ,  H03L7/0814

摘要： Semiconductor devices are disclosed providing synchronization circuits for synchronized signal distribution for a plurality of devices in a semiconductor device. The synchronization apparatus includes an independent synchronization circuit and a dependent synchronization circuit. The independent synchronization circuit may be configured to receive a source signal and to generate a first destination signal substantially synchronized with the source signal. The dependent synchronization circuit may be coupled to the independent synchronization circuit and configured to receive the source signal and to generate a second destination signal substantially synchronized with the source signal.

摘要翻译： 公开了提供用于半导体器件中的多个器件的同步信号分配的同步电路的半导体器件。 同步装置包括独立同步电路和从属同步电路。 独立同步电路可以被配置为接收源信号并产生基本上与源信号同步的第一目的地信号。 依赖同步电路可以耦合到独立同步电路并且被配置为接收源信号并产生与源信号基本同步的第二目的地信号。

公开(公告)号：US20110102020A1

公开(公告)日：2011-05-05

申请号：US12939869

申请日：2010-11-04

申请人： Seong-Hoon Lee

发明人： Seong-Hoon Lee

IPC分类号： G01R25/00

CPC分类号： H03D13/004

摘要： Methods and apparatus are disclosed, such as those involving a digital phase detector that includes a phase detection circuit configured to detect which one of two clock signals leads the other. One such phase detector includes a balancer configured to prepare the phase detection circuit for a phase detection. The phase detection circuit of one or more embodiments includes a cross-coupled latch configured to receive the two clock signals and generate a first latch output and a second latch output in response to the two clock signals. The aforementioned balancer is configured to substantially equalize the voltage levels of the first and second latch outputs before the phase detection circuit detects a phase difference between the two clock signals. For example, the balancer might pre-charge the outputs of the phase detection circuit to substantially the same voltage level before phase detection.

摘要翻译： 公开了诸如涉及数字相位检测器的方法和装置，该数字相位检测器包括被配置为检测两个时钟信号中的哪一个引导另一个的相位检测电路。 一个这样的相位检测器包括配置成准备用于相位检测的相位检测电路的平衡器。 一个或多个实施例的相位检测电路包括交叉耦合锁存器，其配置为接收两个时钟信号，并响应于两个时钟信号产生第一锁存器输出和第二锁存器输出。 上述平衡器被配置为在相位检测电路检测到两个时钟信号之间的相位差之前基本均衡第一和第二锁存器输出的电压电平。 例如，平衡器可以在相位检测之前将相位检测电路的输出预充电至基本相同的电压电平。

公开(公告)号：US20100039147A1

公开(公告)日：2010-02-18

申请号：US12581435

申请日：2009-10-19

申请人： Seong-hoon Lee

发明人： Seong-hoon Lee

IPC分类号： H03L7/00

CPC分类号： H03L7/07 ,  G06F1/10 ,  H03L7/0814

摘要： Semiconductor devices are disclosed providing synchronization circuits for synchronized signal distribution for a plurality of devices in a semiconductor device. The synchronization apparatus includes an independent synchronization circuit and a dependent synchronization circuit. The independent synchronization circuit may be configured to receive a source signal and to generate a first destination signal substantially synchronized with the source signal. The dependent synchronization circuit may be coupled to the independent synchronization circuit and configured to receive the source signal and to generate a second destination signal substantially synchronized with the source signal.

摘要翻译： 公开了提供用于半导体器件中的多个器件的同步信号分配的同步电路的半导体器件。 同步装置包括独立同步电路和从属同步电路。 独立同步电路可以被配置为接收源信号并产生基本上与源信号同步的第一目的地信号。 依赖同步电路可以耦合到独立同步电路并且被配置为接收源信号并产生与源信号基本同步的第二目的地信号。

公开(公告)号：US20090302494A1

公开(公告)日：2009-12-10

申请号：US12271101

申请日：2008-11-14

申请人： Joon Chul Park ,  Jeong Seok Oh ,  Seong Hoon Lee ,  Byung Kwon Min

发明人： Joon Chul Park ,  Jeong Seok Oh ,  Seong Hoon Lee ,  Byung Kwon Min

IPC分类号： B29C47/00

CPC分类号： B60R13/06 ,  B29C48/12 ,  B29C48/30 ,  B29C48/304 ,  B29C48/49 ,  B29L2031/26 ,  B29L2031/30

摘要： There is provided a process of preparing an automotive weatherstrip by co-extrusion of UHMWPE and TPV materials with an SCF. The automotive weatherstrip according to the present invention can be easily recycled, shows excellent properties with respect to lightweight and fire-resistance, and also contributes to improve the product quality by preventing exterior damage.

摘要翻译： 提供了一种通过UHMWPE和TPV材料与SCF共挤出来制备汽车密封条的方法。 根据本发明的汽车密封条可以容易地再循环，在轻质和耐火性方面表现出优异的性能，并且还通过防止外部损坏有助于提高产品质量。

公开(公告)号：US07622970B2

公开(公告)日：2009-11-24

申请号：US12046652

申请日：2008-03-12

申请人： Seong-Hoon Lee

发明人： Seong-Hoon Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/10

摘要： A method and circuitry for a Delay Locked Loop (DLL) or a phase Locked Loop (PLL) is disclosed, which improves the loop stability at high frequencies and allows maximum tracking bandwidth, regardless of process, voltage, or temperature variations. Central to the technique is to effectively operate the loop at a lower frequency close to its own intrinsic bandwidth (1/tLoop) instead of at the higher frequency of the clock signal (1/tCK). To do so, in one embodiment, the loop delay, tLoop, is measured or estimated prior to operation of the loop. The phase detector is then enabled to operate close to the loop frequency, 1/tLoop. In short, the phase detector is made not to see activity during useless delay times, which prevents the loop from overreacting and becoming unstable.

摘要翻译： 公开了用于延迟锁定环（DLL）或锁相环（PLL）的方法和电路，其改善了高频下的环路稳定性，并允许最大跟踪带宽，而不管过程，电压或温度变化。 该技术的核心是以更接近其自身固有带宽（1 / tLoop）的较低频率有效地操作环路，而不是在时钟信号（1 / tCK）的较高频率处。 为了做到这一点，在一个实施例中，在循环操作之前测量或估计环路延迟t L oop。 然后，相位检测器使能接近环路频率1 / tLoop。 简而言之，使相位检测器在无用的延迟时间期间看不到活动，从而防止环路过度反应并变得不稳定。

公开(公告)号：US20090072860A1

公开(公告)日：2009-03-19

申请号：US11854973

申请日：2007-09-13

申请人： Seong-Hoon Lee

发明人： Seong-Hoon Lee

IPC分类号： H03K19/094

CPC分类号： H03K19/01721 ,  H03K19/0005

摘要： Apparatus, methods, and systems include an off-chip driver having an output drive coupled in parallel with the off-chip driver to provide initial drive emphasis for a period of time. The output drive may include a first transistor and a second transistor coupled to an output of the off-chip driver to provide additional initial drive emphasis strength when both transistors are energized for an initial period of time. The time period may be set by an inverted delay circuit.

摘要翻译： 装置，方法和系统包括具有与片外驱动器并联耦合的输出驱动器的片外驱动器，以在一段时间内提供初始驱动强调。 输出驱动器可以包括耦合到片外驱动器的输出的第一晶体管和第二晶体管，以在两个晶体管在初始时间段通电时提供附加的初始驱动强度强度。 该时间段可以由反相延迟电路设置。

公开(公告)号：US07414444B2

公开(公告)日：2008-08-19

申请号：US11489117

申请日：2006-07-18

申请人： Adrian J Drexler ,  Debra M Bell ,  Tyler J Gomm ,  Seong-hoon Lee

发明人： Adrian J Drexler ,  Debra M Bell ,  Tyler J Gomm ,  Seong-hoon Lee

IPC分类号： H03L7/06 ,  H03L7/00

CPC分类号： H03L7/08 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

摘要： Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

公开(公告)号：US07368965B2

公开(公告)日：2008-05-06

申请号：US11489369

申请日：2006-07-18

申请人： Adrian J Drexler ,  Debra M Bell ,  Tyler J Gomm ,  Seong-hoon Lee

发明人： Adrian J Drexler ,  Debra M Bell ,  Tyler J Gomm ,  Seong-hoon Lee

IPC分类号： H03L7/06

CPC分类号： H03L7/08 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

摘要： Clock capturing synchronization circuitry first generates a synchronized clock signal from a reference clock signal, then captures the synchronized clock signal, and continues to output a synchronized clock signal after the reference clock signal is removed. The clock capturing synchronization circuitry also reduces input referred jitter in the synchronized clock signal.

摘要翻译： 时钟捕获同步电路首先从参考时钟信号产生同步的时钟信号，然后捕获同步的时钟信号，并在参考时钟信号被去除之后继续输出同步的时钟信号。 时钟捕获同步电路还减少同步时钟信号中的输入参考抖动。