公开(公告)号：US08505474B2

公开(公告)日：2013-08-13

申请号：US12668930

申请日：2008-07-30

Applicant: Tae Jin Kang ,  Byung Duck Kim ,  Young Seung Chi ,  Jung Sim Roh

Inventor： Tae Jin Kang ,  Byung Duck Kim ,  Young Seung Chi ,  Jung Sim Roh

IPC: D05B3/00 ,  D02G3/36

CPC classification number: D02G3/12 ,  A41D27/00 ,  D02G3/28 ,  D02G3/441 ,  D05C7/06 ,  D10B2331/04 ,  H05K1/038 ,  H05K2201/0281 ,  H05K2201/029

Abstract: The present invention relates to an electrically conductive metal composite embroidery yarn and embroidered circuit using thereof which may be applicable to smart textiles. More particularly, this invention relates to an electrically conductive metal composite embroidery yarn and embroidered circuit for smart textiles which can be used as power supply and signal transmission lines. The present invention provides an embroidered circuit which consists of a metal composite embroidery yarn and a dielectric fabric substrate, wherein the electrically conductive metal composite embroidery yarn is embroidered on the dielectric fabric substrate to form a circuit.

Abstract translation: 本发明涉及可应用于智能纺织品的导电金属复合刺绣线及其使用的绣花电路。 更具体地，本发明涉及可用作电源和信号传输线的智能纺织品的导电金属复合刺绣线和绣花电路。 本发明提供了一种由金属复合刺绣纱线和电介质织物基材组成的绣花线路，其中将导电金属复合刺绣纱线绣在电介质织物基底上以形成电路。

公开(公告)号：US20130059067A1

公开(公告)日：2013-03-07

申请号：US13662739

申请日：2012-10-29

Applicant: Jong-Seong KIM ,  Woo-jae LEE ,  Nam-Seok ROH ,  Sang-IL KIM ,  Min-Ho YOON ,  Young Tak SONG ,  Tae Jin KANG ,  Suk Heung OH ,  Seung-Jae LEE ,  Hye Jin KIM ,  Jin Ju YU ,  Dong Hyun YU ,  Young Sik YOON ,  Jong Hwan LEE

Inventor： Jong-Seong KIM ,  Woo-jae LEE ,  Nam-Seok ROH ,  Sang-IL KIM ,  Min-Ho YOON ,  Young Tak SONG ,  Tae Jin KANG ,  Suk Heung OH ,  Seung-Jae LEE ,  Hye Jin KIM ,  Jin Ju YU ,  Dong Hyun YU ,  Young Sik YOON ,  Jong Hwan LEE

IPC: C12N1/20 ,  B05D5/06 ,  C12P19/04

CPC classification number: C08L1/02 ,  C12N1/20 ,  C12P19/04

Abstract: Disclosed herein is a novel gluconacetobacter strain having cellulose producing activity. Specifically, the present invention relates to a novel gluconacetobacter strain producing nano-structured cellulose in a highly efficient manner. The cellulose produced by the strain, due to its superb thermodynamic properties, can be characterized as nano-structured bacterial cellulose and therefore utilized as a bio-nano-fiber. Particularly, the cellulose can be impregnated with a resin to form a cellulose-based resin which can be effectively adapted for a substrate for a liquid crystal display (LCD).

Abstract translation: 本文公开了具有纤维素生产活性的新颖的葡萄糖酸菌属菌株。 具体地说，本发明涉及以高效的方式生产纳米结构纤维素的新颖的葡糖酸菌属菌株。 该菌株由于其极好的热力学性质而产生的纤维素可以表征为纳米结构的细菌纤维素，因此用作生物纳米纤维。 特别地，纤维素可以用树脂浸渍以形成可以有效地适用于液晶显示器（LCD）的基板的纤维素类树脂。

公开(公告)号：US20120195134A1

公开(公告)日：2012-08-02

申请号：US13356977

申请日：2012-01-24

Applicant: Tae Jin KANG

Inventor： Tae Jin KANG

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C7/1012 ,  G11C7/1072 ,  G11C7/1087

Abstract: A data alignment circuit includes: a select transmission unit configured to selectively transmit a first pulse or ground voltage as a first control pulse and selectively transmit a second pulse or ground voltage as a second control pulse, in response to a control signal; and a data latch unit configured to latch data in response to the first and second pulses and the first and second control pulses, and generate first to fourth data.

Abstract translation: 数据对准电路包括：选择传输单元，被配置为响应于控制信号，选择性地发送作为第一控制脉冲的第一脉冲或接地电压并选择性地传输第二脉冲或接地电压作为第二控制脉冲; 以及数据锁存单元，被配置为响应于所述第一和第二脉冲以及所述第一和第二控制脉冲来锁存数据，并且产生第一到第四数据。

公开(公告)号：US08054709B2

公开(公告)日：2011-11-08

申请号：US12459345

申请日：2009-06-30

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2207/2227

Abstract: A semiconductor memory device comprises a power control circuit for outputting a power voltage in a read operation period and a write operation period, and an internal circuit operating by the power voltage supplied thereto.

Abstract translation: 半导体存储器件包括用于在读操作期间和写操作期间输出电源电压的电源控制电路，以及由供给的电源电压进行工作的内部电路。

公开(公告)号：US20110216911A1

公开(公告)日：2011-09-08

申请号：US13035099

申请日：2011-02-25

Applicant: Tae-Jin KANG

Inventor： Tae-Jin KANG

IPC: H04R1/10

CPC classification number: H01Q1/273 ,  H01Q1/241 ,  H01Q1/46 ,  H01Q1/50 ,  H04M1/6058 ,  H04M1/72522

Abstract: An ear-microphone for connection to a portable apparatus and use as a Frequency Modulation (FM) radio broadcast receiving antenna is provided. The ear-microphone includes an ear plug, a cable, a microphone, and a filtering unit. The ear plug is for connection to an earjack. The cable has a predefined length, has an earphone line whose one end is electrically connected to the ear plug and whose other end is electrically connected to at least one earphone. The microphone intervenes in an intermediate portion of the cable and is connected to the ear plug via a microphone line inside the cable. The filtering unit intervenes in the cable and is installed to have an Electro Static Discharge (ESD) protection function.

Abstract translation: 提供一种用于连接到便携式设备并用作频率调制（FM）无线电广播接收天线的耳麦克风。 耳麦麦克风包括耳塞，电缆，麦克风和过滤单元。 耳塞用于连接耳塞。 电缆具有预定长度，具有耳机线，其一端电连接到耳塞，另一端电连接至至少一个耳机。 麦克风插入电缆的中间部分，并通过电缆内的麦克风线连接到耳塞。 过滤单元插入电缆中，并安装有静电放电（ESD）保护功能。

公开(公告)号：US07777548B2

公开(公告)日：2010-08-17

申请号：US12215774

申请日：2008-06-30

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: H03L5/00

CPC classification number: H03K3/35613 ,  H03K3/012

Abstract: A level shifter includes a level shifting unit for level-shifting an input signal at a first voltage level into a signal at a second voltage level, and an output controller for controlling the level shifting unit to maintain output at a predetermined logic level in response to a deep power down mode signal generated from power which is not turned off in a deep power down mode.

Abstract translation: 电平移位器包括电平移位单元，用于将处于第一电压电平的输入信号电平转换为第二电压电平的信号;以及输出控制器，用于控制电平移位单元，以响应于电平移位单元将输出保持在预定逻辑电平 在深度掉电模式下从未关闭的电源产生的深度掉电模式信号。

公开(公告)号：US07212465B2

公开(公告)日：2007-05-01

申请号：US11077612

申请日：2005-03-11

Applicant: Tae-Jin Kang

Inventor： Tae-Jin Kang

IPC: G11C8/00

CPC classification number: G11C7/222 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1072

Abstract: A clock signal generation apparatus for generating a reference clock signal for outputting data in synchronization with an external clock signal from a semiconductor memory device, including: a clock signal generation unit for receiving an internal clock signal to generate the reference clock signal according to a control signal; and a control unit for generating the control signal based on a read command, a write command and an external address.

Abstract translation: 一种时钟信号产生装置，用于产生用于与来自半导体存储器件的外部时钟信号同步输出数据的参考时钟信号，包括：时钟信号产生单元，用于接收内部时钟信号以根据控制产生参考时钟信号 信号; 以及用于基于读取命令，写入命令和外部地址产生控制信号的控制单元。

公开(公告)号：US07154806B2

公开(公告)日：2006-12-26

申请号：US11122692

申请日：2005-05-05

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: G11C8/00 ,  G11C7/02

CPC classification number: G11C7/06

Abstract: Disclosed herein is a differential amplifier control circuit in which a signal indicating that all banks are not activated is provided to a differential amplifier, so that the differential amplifier does not operate, thereby reducing unnecessary current consumption in an ICC2N situation. An all bank idle notification unit generates an all bank idle signal notifying that a plurality of banks are not activated using a plurality of bank active signals for activating the plurality of the banks. A differential amplifier controller generates a differential amplifier control signal for disabling a differential amplifier using an all bank idle signal and an internal clock signal. The differential amplifier does not operate in response to the differential amplifier control signal if the plurality of the banks is all inactivated.

Abstract translation: 这里公开了一种差分放大器控制电路，其中指示所有存储体未被激活的信号被提供给差分放大器，使得差分放大器不工作，从而减少ICC2N情况下的不必要的电流消耗。 所有存储体空闲通知单元产生通过使用多个用于激活多个存储体的存储体活动信号来激活多个存储体的全部组空闲信号。 差分放大器控制器产生用于使用全部空闲信号和内部时钟信号来禁用差分放大器的差分放大器控制信号。 如果多个存储体全部被去激活，则差分放大器不响应于差分放大器控制信号而不工作。

公开(公告)号：US08854903B2

公开(公告)日：2014-10-07

申请号：US13356977

申请日：2012-01-24

Applicant: Tae Jin Kang

Inventor： Tae Jin Kang

IPC: G11C7/10

CPC classification number: G11C7/1012 ,  G11C7/1072 ,  G11C7/1087

Abstract: A data alignment circuit includes: a select transmission unit configured to selectively transmit a first pulse or ground voltage as a first control pulse and selectively transmit a second pulse or ground voltage as a second control pulse, in response to a control signal; and a data latch unit configured to latch data in response to the first and second pulses and the first and second control pulses, and generate first to fourth data.

Abstract translation: 数据对准电路包括：选择传输单元，被配置为响应于控制信号，选择性地发送作为第一控制脉冲的第一脉冲或接地电压并选择性地传输第二脉冲或接地电压作为第二控制脉冲; 以及数据锁存单元，被配置为响应于所述第一和第二脉冲以及所述第一和第二控制脉冲来锁存数据，并且产生第一到第四数据。

公开(公告)号：US20130222009A1

公开(公告)日：2013-08-29

申请号：US13590885

申请日：2012-08-21

Applicant: Tae Jin KANG

Inventor： Tae Jin KANG

IPC: H03K19/003

CPC classification number: G11C7/1045 ,  G11C7/1057 ,  G11C7/1084

Abstract: Semiconductor modules are provided. The semiconductor module includes a first semiconductor chip configured for storing an information signal that is set in response to a command/address signal and which determines reception of an on-die termination (ODT) signal in a power down mode in response to the information signal to control activation of a first ODT circuit; and a second semiconductor chip configured for sharing and utilizing the first ODT circuit included in the first semiconductor chip.

Abstract translation: 提供半导体模块。 半导体模块包括：第一半导体芯片，其被配置为存储响应于命令/地址信号设置的信息信号，并且响应于信息信号确定在断电模式下接收片上终端（ODT）信号 以控制第一ODT电路的激活; 以及配置为共享和利用包括在第一半导体芯片中的第一ODT电路的第二半导体芯片。