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    DATA ALIGNMENT CIRCUIT
    2.
    发明申请
    DATA ALIGNMENT CIRCUIT 有权
    数据对齐电路

    公开(公告)号：US20120195134A1

    公开(公告)日：2012-08-02

    申请号：US13356977

    申请日：2012-01-24

    Applicant: Tae Jin KANG

    Inventor： Tae Jin KANG

    IPC: G11C7/10 ,  G11C7/00

    CPC classification number: G11C7/1012 ,  G11C7/1072 ,  G11C7/1087

    Abstract: A data alignment circuit includes: a select transmission unit configured to selectively transmit a first pulse or ground voltage as a first control pulse and selectively transmit a second pulse or ground voltage as a second control pulse, in response to a control signal; and a data latch unit configured to latch data in response to the first and second pulses and the first and second control pulses, and generate first to fourth data.

    Abstract translation: 数据对准电路包括：选择传输单元，被配置为响应于控制信号，选择性地发送作为第一控制脉冲的第一脉冲或接地电压并选择性地传输第二脉冲或接地电压作为第二控制脉冲; 以及数据锁存单元，被配置为响应于所述第一和第二脉冲以及所述第一和第二控制脉冲来锁存数据，并且产生第一到第四数据。

    CONTROL SIGNAL GENERATION CIRCUITS, SEMICONDUCTOR MODULES, AND SEMI CONDUCTOR SYSTEMS INCLUDING THE SAME
    3.
    发明申请
    CONTROL SIGNAL GENERATION CIRCUITS, SEMICONDUCTOR MODULES, AND SEMI CONDUCTOR SYSTEMS INCLUDING THE SAME 有权
    控制信号发生电路，半导体模块和包括其中的半导体系统

    公开(公告)号：US20130222009A1

    公开(公告)日：2013-08-29

    申请号：US13590885

    申请日：2012-08-21

    Applicant: Tae Jin KANG

    Inventor： Tae Jin KANG

    IPC: H03K19/003

    CPC classification number: G11C7/1045 ,  G11C7/1057 ,  G11C7/1084

    Abstract: Semiconductor modules are provided. The semiconductor module includes a first semiconductor chip configured for storing an information signal that is set in response to a command/address signal and which determines reception of an on-die termination (ODT) signal in a power down mode in response to the information signal to control activation of a first ODT circuit; and a second semiconductor chip configured for sharing and utilizing the first ODT circuit included in the first semiconductor chip.

    Abstract translation: 提供半导体模块。 半导体模块包括：第一半导体芯片，其被配置为存储响应于命令/地址信号设置的信息信号，并且响应于信息信号确定在断电模式下接收片上终端（ODT）信号 以控制第一ODT电路的激活; 以及配置为共享和利用包括在第一半导体芯片中的第一ODT电路的第二半导体芯片。

    DATA OUTPUT CIRCUIT
    5.
    发明申请
    DATA OUTPUT CIRCUIT 有权
    数据输出电路

    公开(公告)号：US20130176797A1

    公开(公告)日：2013-07-11

    申请号：US13617637

    申请日：2012-09-14

    Applicant: Tae Jin KANG

    Inventor： Tae Jin KANG

    IPC: G11C7/10

    CPC classification number: G11C7/1057 ,  G11C7/1066 ,  G11C7/222

    Abstract: A data output circuit includes a control signal generation block configured to generate a first transfer control signal which is produced in a first read operation and a second transfer control signal which is produced in a second read operation, where the first transfer control signal and the second transfer control signal are generated upon entry into a test mode; and an enable signal generation unit configured to generate first and second enable signals for generating first and second internal clocks, in response to the first and second transfer control signals.

    Abstract translation: 数据输出电路包括：控制信号生成块，被配置为生成在第一读取操作中产生的第一传送控制信号和在第二读取操作中产生的第二传送控制信号，其中第一传送控制信号和第二传送控制信号 传入控制信号在进入测试模式时产生; 以及使能信号生成单元，被配置为响应于第一和第二传送控制信号而产生用于产生第一和第二内部时钟的第一和第二使能信号。

    CLOCK CONTROL CIRCUIT AND CLOCK GENERATION CIRCUIT INCLUDING THE SAME
    6.
    发明申请
    CLOCK CONTROL CIRCUIT AND CLOCK GENERATION CIRCUIT INCLUDING THE SAME 有权
    时钟控制电路和时钟发生电路，包括它们

    公开(公告)号：US20110158032A1

    公开(公告)日：2011-06-30

    申请号：US12824864

    申请日：2010-06-28

    Applicant: Tae Jin KANG

    Inventor： Tae Jin KANG

    IPC: G11C8/18

    CPC classification number: G11C8/18 ,  G11C7/1018 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222

    Abstract: A clock control circuit is presented for reducing unnecessary current consumption. The clock control circuit includes a write enable signal generation unit and a clock enable signal generation unit. The write enable signal generation unit is configured to generate a first write enable signal, which is enabled during a predetermined time period after a write command is inputted, in response to first and second burst signals and a write signal including a pulse generated in response to the write command. The clock enable signal generation unit is configured to generate a clock enable signal, which is enabled during a write operation period, in response to the first write signal and the first write enable signal.

    Abstract translation: 提出了一种时钟控制电路，用于减少不必要的电流消耗。 时钟控制电路包括写使能信号生成单元和时钟使能信号生成单元。 写入使能信号生成单元被配置为响应于第一和第二突发信号而生成第一写入使能信号，该第一写入使能信号在写入命令被输入之后的预定时间段期间被使能，并且写入信号包括响应于 写命令。 时钟使能信号生成单元被配置为响应于第一写入信号和第一写入使能信号而生成在写入操作期间使能的时钟使能信号。

    SEMICONDUCTOR MODULES
    7.
    发明申请
    SEMICONDUCTOR MODULES 有权
    半导体模块

    公开(公告)号：US20130257474A1

    公开(公告)日：2013-10-03

    申请号：US13615373

    申请日：2012-09-13

    Applicant: Tae Jin KANG

    Inventor： Tae Jin KANG

    IPC: H03K19/003

    CPC classification number: H03K19/0005

    Abstract: Semiconductor modules are provided. The semiconductor module includes semiconductor chips with one or more ranks. The semiconductor module includes a mode register configured for storing a first information signal whose logic level is set or determined according to a number of the ranks and an on-die termination (ODT) controller configured for generating an internal control signal for activating an ODT circuit in response to the first information signal. The internal control signal is enabled during a read operation or disabled during a write operation.

    Abstract translation: 提供半导体模块。 半导体模块包括具有一个或多个等级的半导体芯片。 半导体模块包括模式寄存器，其被配置为存储根据等级的数量来设置或确定其逻辑电平的第一信息信号，以及配置用于产生用于激活ODT电路的内部控制信号的片上终端（ODT）控制器 响应于第一信息信号。 内部控制信号在读操作期间被使能，或者在写操作期间被禁止。

    SEMICONDUCTOR INTEGRATED CIRCUIT
    8.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    半导体集成电路

    公开(公告)号：US20120169380A1

    公开(公告)日：2012-07-05

    申请号：US13243351

    申请日：2011-09-23

    Applicant: Tae Jin KANG

    Inventor： Tae Jin KANG

    IPC: H03K3/00

    CPC classification number: G11C7/1057 ,  G11C7/1051 ,  H03K19/018521 ,  H03K19/018585

    Abstract: A semiconductor integrated circuit includes a first output driver configured to drive a first comparison signal, which is generated by comparing a voltage of a pad coupled to an external resistor with an upper-limit reference voltage, according to drivability determined by a pull-up code and a pull-down code, and output the driven signal as first output data; and a second output driver configured to drive a second comparison signal, which is generated by comparing the voltage of the pad with a lower-limit reference voltage, according to the drivability determined by the pull-up code and the pull-down code, and output the driven signal as second output data.

    Abstract translation: 半导体集成电路包括：第一输出驱动器，被配置为驱动第一比较信号，该第一比较信号是通过将耦合到外部电阻器的焊盘的电压与上限参考电压进行比较而产生的，根据由上拉代码确定的驱动能力 和下拉代码，并将驱动信号作为第一输出数据输出; 以及第二输出驱动器，被配置为根据由所述上拉代码和所述下拉码确定的驾驶性能来驱动通过将所述垫的电压与下限参考电压进行比较而产生的第二比较信号，以及 输出驱动信号作为第二输出数据。

    WRITE DRIVING DEVICE
    9.
    发明申请
    WRITE DRIVING DEVICE 有权
    写驱动器

    公开(公告)号：US20110128049A1

    公开(公告)日：2011-06-02

    申请号：US12939614

    申请日：2010-11-04

    Applicant: Tae Jin KANG

    Inventor： Tae Jin KANG

    IPC: H03K3/00

    CPC classification number: H03M9/00 ,  G11C7/1087 ,  G11C7/1096 ,  H03K3/356121 ,  H03K5/1534

    Abstract: A write driving device includes a buffer unit, a duration signal generation unit, and a data input clock pulse generation unit. The buffer unit is configured to generate an alignment signal in response to a transition timing of a data strobe signal. The duration signal generation unit is configured to generate a duration signal which is enabled during a predetermined duration in response to a write command. The data input clock pulse generation unit is configured to generate a data input clock pulse for transferring data to a global line in response to the alignment signal within an enable duration of the duration signal.

    Abstract translation: 写驱动装置包括缓冲单元，持续时间信号生成单元和数据输入时钟脉冲生成单元。 缓冲单元被配置为响应于数据选通信号的转变定时产生对准信号。 持续时间信号生成单元被配置为产生响应于写入命令在预定持续时间期间使能的持续时间信号。 数据输入时钟脉冲生成单元被配置为响应于持续时间信号的使能持续时间内的对准信号，生成用于将数据传送到全局线的数据输入时钟脉冲。

    SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR SYSTEM
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR SYSTEM 有权
    半导体存储器件和半导体系统

    公开(公告)号：US20130114347A1

    公开(公告)日：2013-05-09

    申请号：US13336876

    申请日：2011-12-23

    Applicant: Tae Jin KANG

    Inventor： Tae Jin KANG

    IPC: G11C7/10 ,  G11C7/00 ,  G11C29/00

    CPC classification number: G11C29/56008 ,  G11C29/56012

    Abstract: A semiconductor system includes a semiconductor memory device configured to, during a test mode, store received data in a memory cell in response to a write command, read the stored data as information data in response to a read command, and internally store the information data, in response to the read command, in synchronization with a pulse generated when a level of the information data changes.

    Abstract translation: 半导体系统包括：半导体存储器件，被配置为在测试模式期间响应于写入命令将接收到的数据存储在存储器单元中，响应于读取命令读取存储的数据作为信息数据，并在内部存储信息数据 响应于读取命令，与信息数据的级别变化时产生的脉冲同步。

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