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    Method and apparatus for an active negative-capacitor circuit to cancel the input capacitance of comparators
    41.
    发明授权
    Method and apparatus for an active negative-capacitor circuit to cancel the input capacitance of comparators 有权
    用于消除比较器的输入电容的有源负电容电路的方法和装置

    公开(公告)号：US09264056B2

    公开(公告)日：2016-02-16

    申请号：US14672214

    申请日：2015-03-29

    Applicant: Tensorcom, Inc.

    Inventor： Dai Dai

    IPC: H03M1/12 ,  H03M1/00 ,  H03K5/24 ,  H03M1/08 ,  H03M1/18 ,  H03H11/48

    CPC classification number: H03K5/2481 ,  H03H11/481 ,  H03M1/002 ,  H03M1/0836 ,  H03M1/0845 ,  H03M1/183

    Abstract: The differential output of a Programmable Gain Amplifier (PGA) is loaded by the input differential gate capacitance of a plurality of Analog to Digital convertors (ADC) comparators and the differential metal layer traces to interconnect these comparators to the PGA. The differential capacitive load presented to the PGA is quite large and reduces the bandwidth of this interconnect between the PGA and ADC. To overcome the performance degradation due to the differential capacitive load, an active negative-capacitor circuit cancels the effect of the large input capacitance of the ADC comparators. This cancelation extends the gain characteristics of the interconnect between the PGA's output and the inputs of the first stage of the comparators. The active negative-capacitance is comprised of a cross pair NMOS with a capacitor connecting their sources where each NMOS is biased by a current source.

    Abstract translation: 可编程增益放大器（PGA）的差分输出由多个模数转换器（ADC）比较器的输入差分栅极电容和差分金属层迹线加载，以将这些比较器与PGA互连。 提供给PGA的差分电容性负载相当大，并降低了PGA和ADC之间的这种互连的带宽。 为了克服由于差分电容性负载引起的性能下降，有源负电容电路消除了ADC比较器的大输入电容的影响。 该取消扩展了PGA输出与比较器的第一级的输入之间的互连的增益特性。 有源负电容由交叉对NMOS组成，其中电容器连接其源极，其中每个NMOS由电流源偏置。

    Method and Apparatus of a Fully-Pipelined Layered LDPC Decoder
    42.
    发明申请
    Method and Apparatus of a Fully-Pipelined Layered LDPC Decoder 有权
    全流水线分层LDPC解码器的方法和装置

    公开(公告)号：US20150214980A1

    公开(公告)日：2015-07-30

    申请号：US14165505

    申请日：2014-01-27

    Applicant: Tensorcom, Inc.

    Inventor： Bo Xia ,  Ricky Lap Kei Cheung ,  Bo Lu

    IPC: H03M13/11

    CPC classification number: H03M13/1145 ,  H03M13/1122 ,  H03M13/114 ,  H03M13/1148 ,  H03M13/116

    Abstract: The architecture is able to switch to Non-blocking check-node-update (CNU) scheduling architecture which has better performance than blocking CNU scheduling architecture. The architecture uses an Offset Min-Sum with Beta=1 with a clock domain operating at 440 MHz. The constraint macro-matrix is a spare matrix where each “1’ corresponds to a sub-array of a cyclically shifted identity matrix which is a shifted version of an identity matrix. Four core processors are used in the layered architecture where the constraint matrix uses a sub-array of 42 (check nodes)×42 (variable nodes) in the macro-array of 168×672 bits. Pipeline processing is used where the delay for each layer only requires 4 clock cycles.

    Abstract translation: 该架构能够切换到具有比阻塞CNU调度架构更好的性能的非阻塞校验节点更新（CNU）调度体系结构。 该架构使用Beta = 1的偏移最小和，时钟域工作在440 MHz。 约束宏矩阵是备用矩阵，其中每个“1”对应于作为单位矩阵的移位版本的循环移位单位矩阵的子阵列。 在分层架构中使用四个核心处理器，约束矩阵在168×672位的宏阵列中使用42（校验节点）×42（变量节点）的子阵列。 使用管道处理，其中每层的延迟只需要4个时钟周期。

    Gilbert mixer with negative gm to increase NMOS mixer conversion
    43.
    发明授权
    Gilbert mixer with negative gm to increase NMOS mixer conversion 有权
    吉尔伯特混频器采用负gm来增加NMOS混频器的转换

    公开(公告)号：US08836407B1

    公开(公告)日：2014-09-16

    申请号：US13789681

    申请日：2013-03-08

    Applicant: Tensorcom, Inc.

    Inventor： Zaw Soe ,  Tham KhongMeng

    IPC: G06F7/44 ,  G06G7/16

    CPC classification number: G06G7/16 ,  H03D7/1441 ,  H03D7/1458 ,  H03D7/165 ,  H03D2200/0019

    Abstract: A cross coupled NMOS transistors providing a negative gm transistor feedback allows a mixer to saturate at a reduced input signal swing voltage when compared to a conventional mixer allowing the mixer to enter into the current mode operation at a reduced signal input voltage range. The linearity of the baseband signal path can be traded against the mixer gain and is improved if the signal swing in the baseband signal path is reduced. The input mixer transistors operate in the saturated mode at a reduced input signal swing voltage causing the power efficiency of the system to increase since the transmit chain operates at a class-D power efficient. Efficiency is very important in mobile applications to save and extend the battery power of a mobile phone providing a better utilization of the available power since most of that power is supplied to the energy of the outgoing modulated signal.

    Abstract translation: 提供负gm晶体管反馈的交叉耦合NMOS晶体管使混频器能够与传统的混频器相比，作为降低的输入信号摆幅电压饱和，从而允许混频器在降低的信号输入电压范围内进入电流模式操作。 基带信号路径的线性度可以抵抗混频器增益进行交易，如果基带信号路径中的信号摆幅减小，则可以得到改善。 输入混频器晶体管以降低的输入信号摆幅电压在饱和模式下工作，导致系统的功率效率增加，因为发射链以D类功率有效工作。 在移动应用中，效率对于节省和扩展移动电话的电池电力是非常重要的，其提供了对可用功率的更好的利用，因为大部分功率被提供给输出调制信号的能量。

    Method and apparatus of a fully-pipelined layered LDPC decoder
    46.
    发明授权
    Method and apparatus of a fully-pipelined layered LDPC decoder 有权

    公开(公告)号：US10778250B2

    公开(公告)日：2020-09-15

    申请号：US16277890

    申请日：2019-02-15

    Applicant: TensorCom, Inc.

    Inventor： Bo Xia ,  Ricky Lap Kei Cheung ,  Bo Lu

    IPC: H03M13/11

    Abstract: Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.

    METHOD AND APPARATUS OF A FULLY-PIPELINED LAYERED LDPC DECODER
    47.
    发明申请
    METHOD AND APPARATUS OF A FULLY-PIPELINED LAYERED LDPC DECODER 审中-公开

    公开(公告)号：US20190222227A1

    公开(公告)日：2019-07-18

    申请号：US16277890

    申请日：2019-02-15

    Applicant: TensorCom, Inc.

    Inventor： Bo Xia ,  Ricky Lap Kei Cheung ,  Bo Lu

    IPC: H03M13/11

    CPC classification number: H03M13/1145 ,  H03M13/1122 ,  H03M13/114 ,  H03M13/1148 ,  H03M13/116

    Abstract: Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.

    Method and apparatus of a fully-pipelined layered LDPC decoder
    48.
    发明授权
    Method and apparatus of a fully-pipelined layered LDPC decoder 有权

    公开(公告)号：US10250280B2

    公开(公告)日：2019-04-02

    申请号：US15011252

    申请日：2016-01-29

    Applicant: Tensorcom, Inc.

    Inventor： Bo Xia ,  Ricky Lap Kei Cheung ,  Bo Lu

    IPC: H03M13/11

    Abstract: Processors are arranged in a pipeline structure to operate on multiple layers of data, each layer comprising multiple groups of data. An input to a memory is coupled to an output of the last processor in the pipeline, and the memory's output is coupled to an input of the first processor in the pipeline. Multiplexing and de-multiplexing operations are performed in the pipeline. For each group in each layer, a stored result read from the memory is applied to the first processor in the pipeline structure. A calculated result of the stored result is output at the last processor and stored in the memory. Once processing for the last group of data in a first layer is completed, the corresponding processor is configured to process data in a next layer before the pipeline finishes processing the first layer. The stored result obtained from the next layer comprises a calculated result produced from a layer previous to the first layer.

    Direct Coupled Biasing Circuit for High Frequency Applications
    49.
    发明申请
    Direct Coupled Biasing Circuit for High Frequency Applications 审中-公开

    公开(公告)号：US20170310308A1

    公开(公告)日：2017-10-26

    申请号：US15646776

    申请日：2017-07-11

    Applicant: Tensorcom, Inc.,

    Inventor： Zaw Soe ,  KhongMeng Tham

    IPC: H03K3/012 ,  H03K17/56 ,  H01Q1/50 ,  H04B5/00 ,  G05F3/16

    CPC classification number: H03K3/012 ,  G05F3/16 ,  H01Q1/50 ,  H03K17/56 ,  H04B5/0075

    Abstract: This invention eliminates the need for “capacitor coupling” or “transformer coupling,” and the associated undesirable parasitic capacitance and inductance associated with these coupling techniques when designing high frequency (˜60 GHz) circuits. At this frequency, the distance between two adjacent stages needs to be minimized. A resonant circuit in series with the power or ground leads is used to isolate a biasing signal from a high frequency signal. The introduction of this resonant circuit allows a first stage to be “directly coupled” to a next stage using a metallic trace. The “direct coupling” technique passes both the high frequency signal and the biasing voltage to the next stage. The “direct coupling” approach overcomes the large die area usage when compared to either the “AC coupling” or “transformer coupling” approach since neither capacitors nor transformers are required to transfer the high frequency signals between stages.

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