公开(公告)号：US08446189B2

公开(公告)日：2013-05-21

申请号：US12794227

申请日：2010-06-04

Applicant: Yu-Pin Chou ,  Hsien-Chun Chang ,  Wen-Che Wu

Inventor： Yu-Pin Chou ,  Hsien-Chun Chang ,  Wen-Che Wu

IPC: H03L7/00

CPC classification number: H03K17/20

Abstract: A power-on reset circuit includes a clamping signal generator and a determining device. The clamping signal generator is adapted to receive a trigger signal, and generates a clamping signal with reference to the trigger signal. The clamping signal generator includes an output unit for generating the clamping signal according to a feedback signal, and a feedback unit for generating the feedback signal according to first and second intermediate signals. The first intermediate signal is generated with reference to the clamping signal. The second intermediate signal is generated according to the trigger signal. The determining device is adapted to receive the trigger signal, is coupled to the clamping signal generator for receiving the clamping signal therefrom, and is operable to generate a reset signal according to the trigger signal and the clamping signal.

Abstract translation: 上电复位电路包括钳位信号发生器和确定装置。 钳位信号发生器适于接收触发信号，并且参考触发信号产生钳位信号。 钳位信号发生器包括用于根据反馈信号产生钳位信号的输出单元和用于根据第一和第二中间信号产生反馈信号的反馈单元。 参考钳位信号产生第一中间信号。 根据触发信号产生第二中间信号。 确定装置适于接收触发信号，耦合到钳位信号发生器用于从其接收钳位信号，并且可操作以根据触发信号和钳位信号产生复位信号。

公开(公告)号：US08180932B2

公开(公告)日：2012-05-15

申请号：US12125075

申请日：2008-05-22

Applicant: An-Ming Lee ,  Tzu-Chien Tzeng ,  Yu-Pin Chou ,  Tzuo-Bo Lin

Inventor： An-Ming Lee ,  Tzu-Chien Tzeng ,  Yu-Pin Chou ,  Tzuo-Bo Lin

IPC: G06F3/00

CPC classification number: H04L25/0272 ,  H04L25/0262

Abstract: The present invention discloses a signal receiving method for determining a transmission format of an input signal and a related signal receiving circuit. The signal receiving method includes: receiving the input signal; generating a signal detecting result corresponding to at least a signal transmission channel of a plurality of signal transmission channels according to an output result of the signal transmission channel; and determining the transmission format of the input signal according to the signal detecting result. The signal receiving circuit includes: an input interface, for receiving an input signal; a detecting module, for generating a signal detecting result corresponding to at least a signal transmission channel of a plurality of signal transmission channels according to an output result of the signal transmission channel; and a determining unit, for determining the transmission format of the input signal according to the signal detecting result.

Abstract translation: 本发明公开了一种用于确定输入信号和相关信号接收电路的传输格式的信号接收方法。 信号接收方法包括：接收输入信号; 根据所述信号传输通道的输出结果产生与至少多个信号传输通道的信号传输通道相对应的信号检测结果; 以及根据信号检测结果确定输入信号的传输格式。 信号接收电路包括：输入接口，用于接收输入信号; 检测模块，用于根据所述信号传输通道的输出结果产生与至少多个信号传输通道的信号传输通道相对应的信号检测结果; 以及确定单元，用于根据信号检测结果确定输入信号的传输格式。

公开(公告)号：US20100308877A1

公开(公告)日：2010-12-09

申请号：US12794227

申请日：2010-06-04

Applicant: Yu-Pin Chou ,  Hsien-Chun Chang ,  Wen-Che Wu

Inventor： Yu-Pin Chou ,  Hsien-Chun Chang ,  Wen-Che Wu

IPC: H03L7/00

CPC classification number: H03K17/20

Abstract: A power-on reset circuit includes a clamping signal generator and a determining device. The clamping signal generator is adapted to receive a trigger signal, and generates a clamping signal with reference to the trigger signal. The clamping signal generator includes an output unit for generating the clamping signal according to a feedback signal, and a feedback unit for generating the feedback signal according to first and second intermediate signals. The first intermediate signal is generated with reference to the clamping signal. The second intermediate signal is generated according to the trigger signal. The determining device is adapted to receive the trigger signal, is coupled to the clamping signal generator for receiving the clamping signal therefrom, and is operable to generate a reset signal according to the trigger signal and the clamping signal.

Abstract translation: 上电复位电路包括钳位信号发生器和确定装置。 钳位信号发生器适于接收触发信号，并且参考触发信号产生钳位信号。 钳位信号发生器包括用于根据反馈信号产生钳位信号的输出单元和用于根据第一和第二中间信号产生反馈信号的反馈单元。 参考钳位信号产生第一中间信号。 根据触发信号产生第二中间信号。 确定装置适于接收触发信号，耦合到钳位信号发生器用于从其接收钳位信号，并且可操作以根据触发信号和钳位信号产生复位信号。

公开(公告)号：US20100003927A1

公开(公告)日：2010-01-07

申请号：US12496237

申请日：2009-07-01

Applicant: Yu-Pin CHOU ,  Tzuo-Bo LIN ,  Chih-Ming LEE

Inventor： Yu-Pin CHOU ,  Tzuo-Bo LIN ,  Chih-Ming LEE

IPC: H04B1/00

CPC classification number: G09G5/006 ,  G09G2330/022

Abstract: Disclosed is an apparatus and method of power-saving and wake-up, which is not only used to reduce the power consumption of a system of electronic equipment, but also allow the system to immediately return to normal operation according to the requirement. The apparatus for power-saving and wake-up includes a first detector, a second detector, a decoder and a third detector. The method for power-saving and wake-up includes detecting a cable signal, a clock pair signal and a differential pair signal. When one of the detected signals is unusual, the system soon turns off the unusual channel power and implement the procedures for power saving and operates under the power saving mode, which can realize the effect of power saving and low power consumption. The method for power-saving and wake-up includes detecting the cable signal, the toggling and frequency of the clock signal and the synchronizing signals of the system.

Abstract translation: 本发明公开了一种省电唤醒的装置和方法，不仅用于降低电子设备系统的功耗，而且可以根据需要立即恢复正常运行。 用于省电和唤醒的装置包括第一检测器，第二检测器，解码器和第三检测器。 省电和唤醒的方法包括检测电缆信号，时钟对信号和差分对信号。 当其中一个检测到的信号异常时，系统即将关闭异常通道电源，实现节电程序，并在省电模式下工作，实现省电，低功耗的效果。 节电和唤醒的方法包括检测电缆信号，时钟信号的切换和频率以及系统的同步信号。

公开(公告)号：US20080048740A1

公开(公告)日：2008-02-28

申请号：US11773940

申请日：2007-07-05

Applicant: Yu-Pin Chou

Inventor： Yu-Pin Chou

IPC: H03L7/06

CPC classification number: H03L7/081

Abstract: The present invention relates to an apparatus and a method thereof for generating a clock signal. The apparatus includes a clock generating module and at least one delay stage. The clock generating module receives a reference signal through a first signal path, receives a feedback signal through a second signal path, and provides a clock signal to a third signal path according to the reference signal, wherein the feedback signal corresponds to the clock signal. The at least one delay stage is located on at least one of the first, second, and third signal paths for providing a corresponding delay on the signal path at which the at least one delay stage is positioned.

Abstract translation: 本发明涉及一种用于产生时钟信号的装置及其方法。 该装置包括时钟产生模块和至少一个延迟级。 时钟产生模块通过第一信号路径接收参考信号，通过第二信号路径接收反馈信号，并根据参考信号向第三信号路径提供时钟信号，其中反馈信号对应于时钟信号。 所述至少一个延迟级位于所述第一，第二和第三信号路径中的至少一个上，用于在所述至少一个延迟级所位于的信号路径上提供对应的延迟。

公开(公告)号：US20080032658A1

公开(公告)日：2008-02-07

申请号：US11882039

申请日：2007-07-30

Applicant: Jui-Yuan Tsai ,  Yu-Pin Chou

Inventor： Jui-Yuan Tsai ,  Yu-Pin Chou

IPC: H04B1/26

CPC classification number: H04N9/64

Abstract: The invention discloses an analog front end device comprising a band-gap voltage reference circuit and at least one conversion circuit, wherein the conversion circuit includes a clamper, an input buffer, a low-pass filter, a high frequency gain unit and an analog to digital converter. The analog front end device utilize a high frequency gain unit to increase high frequency gain of the image analog signal for increasing the usable number of sampling phase of the image analog signal.

Abstract translation: 本发明公开了一种包括带隙电压参考电路和至少一个转换电路的模拟前端装置，其中转换电路包括钳位器，输入缓冲器，低通滤波器，高频增益单元和模拟 - 数字转换器。 模拟前端装置利用高频增益单元增加图像模拟信号的高频增益，以增加图像模拟信号的可用采样相位数。

公开(公告)号：US07280091B2

公开(公告)日：2007-10-09

申请号：US11279251

申请日：2006-04-11

Applicant: Chi-Feng Wang ,  Jui-Yuan Tsai ,  Yu-Pin Chou ,  Jin-Sheng Gong

Inventor： Chi-Feng Wang ,  Jui-Yuan Tsai ,  Yu-Pin Chou ,  Jin-Sheng Gong

IPC: G09G3/36 ,  H03M1/06

CPC classification number: G09G5/04 ,  G09G3/2092

Abstract: An analog front-end (AFE) circuit of a digital display is disclosed including: a first circuit to intermittently invert a working clock to generate a control signal and to generate a sampling signal, wherein the sampling signal is corresponding to the working clock; a first analog-to-digital converter (ADC) coupled to the first circuit for converting an analog video signal into a first digital video signal according to the sampling signal; a second analog-to-digital converter coupled to the first circuit for converting the analog video signal into a second digital video signal according to the sampling signal; and a first multiplexer for selectively outputting the first digital video signal or the second digital video signal according to the control signal.

Abstract translation: 公开了一种数字显示器的模拟前端（AFE）电路，包括：第一电路，间歇地反转工作时钟以产生控制信号并产生采样信号，其中采样信号对应于工作时钟; 耦合到第一电路的第一模数转换器（ADC），用于根据采样信号将模拟视频信号转换成第一数字视频信号; 耦合到第一电路的第二模数转换器，用于根据采样信号将模拟视频信号转换成第二数字视频信号; 以及第一多路复用器，用于根据控制信号选择性地输出第一数字视频信号或第二数字视频信号。

公开(公告)号：US20070159263A1

公开(公告)日：2007-07-12

申请号：US11620053

申请日：2007-01-05

Applicant: Yu-Pin Chou ,  Chi-Kung Kuan

Inventor： Yu-Pin Chou ,  Chi-Kung Kuan

IPC: H03L7/00

CPC classification number: H03L7/10 ,  H03L7/0814 ,  H03L7/0891 ,  H03L7/0991 ,  H03L7/0996 ,  H03L2207/06 ,  Y10S331/02

Abstract: A phase-locked loop (PLL) for rapid lock-in applicable to digital, analog, or hybrid digital-analog PLL circuits is provided. Besides the units for basic operation, including a phase-frequency detector (PFD), a charge pump, a loop filter, and/or a voltage/current/digital-controlled oscillator (VCO/ICO/DCO), an additional lock-in actuator circuit is provided for providing lock-in signals, achieving the purpose of rapid lock-in through operational processes.

Abstract translation: 提供了适用于数字，模拟或混合数字 - 模拟PLL电路的快速锁定锁相环（PLL）。 除了用于基本操作的单元，包括相位频率检测器（PFD），电荷泵，环路滤波器和/或电压/电流/数字控制振荡器（VCO / ICO / DCO），附加锁定 致动器电路被提供用于提供锁定信号，实现通过操作过程快速锁定的目的。

公开(公告)号：US20060220687A1

公开(公告)日：2006-10-05

申请号：US11277361

申请日：2006-03-24

Applicant: Hung-Jen Chu ,  Chao-Hsin Lu ,  Shiu-Rong Tong ,  Yu-Pin Chou

Inventor： Hung-Jen Chu ,  Chao-Hsin Lu ,  Shiu-Rong Tong ,  Yu-Pin Chou

IPC: H03K19/00

CPC classification number: G06F1/22 ,  H03K19/1732

Abstract: A chip with an adjustable pinout function is disclosed. The chip includes a first pinout, a second pinout, a logic circuit, and a selecting circuit. The logic circuit includes a first port and a second port. The selecting circuit, which is coupled to the logic circuit, the first pinout, and the second pinout, controls the first pinout to be coupled to the first port or the second port, and controls the second pinout to be coupled to the first port or the second port.

Abstract translation: 公开了一种具有可调节引脚排列功能的芯片。 芯片包括第一引脚，第二引脚，逻辑电路和选择电路。 逻辑电路包括第一端口和第二端口。 耦合到逻辑电路，第一引脚排列和第二引脚分布的选择电路控制第一引脚被耦合到第一端口或第二端口，并且控制第二引脚分布以耦合到第一端口或 第二个港口。

公开(公告)号：US20060136620A1

公开(公告)日：2006-06-22

申请号：US10905109

申请日：2004-12-16

Applicant: Yu-Pin Chou

Inventor： Yu-Pin Chou

IPC: G06F3/06

CPC classification number: G06F5/06

Abstract: A data transfer interface apparatus and method for controlling data transfer. The data transfer interface apparatus includes a first storage unit for storing an input data according to a first clock and for outputting a first output data according to a second clock, a single-port memory coupled to the first storage unit for storing the first output data according to the second clock and for outputting a second output data according to the second clock, and a second storage unit coupled to the single-port memory for storing the second output data according to the second clock and for outputting a third output data according to a third clock.

Abstract translation: 一种用于控制数据传送的数据传输接口装置和方法。 数据传输接口装置包括：第一存储单元，用于根据第一时钟存储输入数据，并用于根据第二时钟输出第一输出数据;耦合到第一存储单元的单端口存储器，用于存储第一输出数据 并且根据第二时钟输出第二输出数据，以及第二存储单元，其耦合到单端口存储器，用于根据第二时钟存储第二输出数据，并根据第二时钟输出第三输出数据 第三个时钟。