公开(公告)号：US20180165872A1

公开(公告)日：2018-06-14

申请号：US15374752

申请日：2016-12-09

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Laurent Lefebvre ,  Michael Mantor ,  Mark Fowler ,  Mikko Alho ,  Mika Tuomi ,  Kiia Kallio ,  Patrick Klas Rudolf Buss ,  Jari Antero Komppa ,  Kaj Tuomi ,  Christopher J. Brennan

IPC: G06T15/40 ,  G06T15/80

CPC classification number: G06T15/405 ,  G06T11/40 ,  G06T15/005 ,  G06T15/80

Abstract: Techniques for removing or identifying overlapping fragments in a fragment stream after z-culling are disclosed. The techniques include maintaining a first-in-first-out buffer that stores post-z-cull fragments. Each time a new fragment is received at the buffer, the screen position of the fragment is checked against all other fragments in the buffer. If the screen position of the fragment matches the screen position of a fragment in the buffer, then the fragment in the buffer is removed or marked as overlapping. If the screen position of the fragment does not match the screen position of any fragment in the buffer, then no modification is performed to fragments already in the buffer. In either case, he fragment is added to the buffer. The contents of the buffer are transmitted to the pixel shader for pixel shading at a later time.

公开(公告)号：US20170076421A1

公开(公告)日：2017-03-16

申请号：US15362230

申请日：2016-11-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Robert Scott Hartog ,  Ralph Clayton Taylor ,  Michael Mantor ,  Kevin John McGrath ,  Sebastien Nussbaum ,  Nuwan Jayasena ,  Rex McCrary ,  Mark Leather ,  Philip J. Rogers ,  Thomas Woller

IPC: G06T1/20 ,  G06F9/52 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06F9/4881 ,  G06F9/526 ,  G06T1/60

Abstract: Methods and apparatus are described. A method includes an accelerated processing device running a process. When a maximum time interval during which the process is permitted to run expires before the process completes, the accelerated processing device receives an operating-system-initiated instruction to stop running the process. The accelerated processing device stops the process from running in response to the received operating-system-initiated instruction.

Abstract translation: 描述了方法和装置。 一种方法包括运行处理的加速处理装置。 当进程完成之前允许进程允许的最大时间间隔到期时，加速处理装置接收操作系统启动的指令以停止运行该进程。 加速处理装置响应于接收到的操作系统发起的指令而停止进程运行。

公开(公告)号：US20250068464A1

公开(公告)日：2025-02-27

申请号：US18940931

申请日：2024-11-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthaeus G. Chajdas ,  Christopher J. Brennan ,  Michael Mantor ,  Robert W. Martin ,  Nicolai Haehnle

IPC: G06F9/48

Abstract: A method for hierarchical work scheduling includes consuming a work item at a first scheduling domain having a local scheduler circuit and one or more workgroup processing elements. Consuming the work item produces a set of new work items. Subsequently, the local scheduler circuit distributes at least one new work item of the set of new work items to be executed locally at the first scheduling domain. If the local scheduler circuit of the first scheduling domain determines that the set of new work items includes one or more work items that would overload the first scheduling domain with work if scheduled for local execution, those work items are distributed to the next higher-level scheduler circuit in a scheduling domain hierarchy for redistribution to one or more other scheduling domains.

公开(公告)号：US20250068429A1

公开(公告)日：2025-02-27

申请号：US18536982

申请日：2023-12-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Stephen Junkins ,  Christopher J. Brennan ,  Ian Richard Beaumont ,  Kellie Marks ,  Matthaeus G. Chajdas ,  Max Oberberger ,  Michael John Bedy ,  Michael Mantor ,  Sean Keely

IPC: G06F9/38

Abstract: A Streaming Wave Coalescer (SWC) circuit stores a first set of state values associated with a first subset of threads of a first wave in a bin based on each of the first subset of threads including a first set of instructions to be executed. A second set of state values associated with a second subset of threads of a second wave is stored in the bin based on each of the second subset of threads including the first set of instructions to be executed and based on the first wave and the second wave both being associated with a hard key. A third wave is formed from the threads of the first subset and the second subset and is emitted for execution. As a result of reorganizing the threads and reconstituting a different wave, thread divergence of waves sent for execution is reduced.

公开(公告)号：US12217021B2

公开(公告)日：2025-02-04

申请号：US18219268

申请日：2023-07-07

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Bin He ,  Shubh Shah ,  Michael Mantor

IPC: G06F7/57 ,  G06F17/16 ,  G06N3/08

Abstract: A parallel processing unit employs an arithmetic logic unit (ALU) having a relatively small footprint, thereby reducing the overall power consumption and circuit area of the processing unit. To support the smaller footprint, the ALU includes multiple stages to execute operations corresponding to a received instruction. The ALU executes at least one operation at a precision indicated by the received instruction, and then reduces the resulting data of the at least one operation to a smaller size before providing the results to another stage of the ALU to continue execution of the instruction.

公开(公告)号：US20240424407A1

公开(公告)日：2024-12-26

申请号：US18749065

申请日：2024-06-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Karthik Mohan Kumar ,  Michael Mantor ,  Pedro Antonio Pena ,  Archana Ramalingam

IPC: A63F13/67 ,  G06F40/284

Abstract: Systems and techniques for generating and animating non-player characters (NPCs) within virtual digital environments are provided. Multimodal input data is received that comprises a plurality of input modalities for interaction with an NPC having a set of body features and a set of facial features. The multimodal input data is processed through one or more neural networks to generate animation sequences for both the body features and facial features of the NPC. Generating such animation sequences includes disentangling the multimodal input data to generate substantially disentangled latent representations, combining these representations with the multimodal input data, and using a large-language model (LLM) to generate speech data for the NPC. Further processing using reverse diffusion generates face vertex displacement data and joint trajectory data based on the combined representation and generated speech data. The face vertex displacement data, joint trajectory data, and speech data are used to produce an animated representation of the NPC, which is then provided to environment-specific adapters to animate the NPC within a virtual digital environment.

公开(公告)号：US12032487B2

公开(公告)日：2024-07-09

申请号：US17666974

申请日：2022-02-08

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI Technologies ULC

Inventor： Benjamin T. Sander ,  Mark Fowler ,  Anthony Asaro ,  Gongxian Jeffrey Cheng ,  Michael Mantor

IPC: G06F12/10 ,  G06F12/0893 ,  G06F12/1027

CPC classification number: G06F12/1027 ,  G06F12/0893 ,  G06F2212/684

Abstract: A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.

公开(公告)号：US20240111578A1

公开(公告)日：2024-04-04

申请号：US17957714

申请日：2022-09-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Matthaeus G. Chajdas ,  Christopher J. Brennan ,  Michael Mantor ,  Robert W. Martin ,  Nicolai Haehnle

IPC: G06F9/48

CPC classification number: G06F9/4881

Abstract: A method for hierarchical work scheduling includes consuming a work item at a first scheduling domain having a local scheduler circuit and one or more workgroup processing elements. Consuming the work item produces a set of new work items. Subsequently, the local scheduler circuit distributes at least one new work item of the set of new work items to be executed locally at the first scheduling domain. If the local scheduler circuit of the first scheduling domain determines that the set of new work items includes one or more work items that would overload the first scheduling domain with work if scheduled for local execution, those work items are distributed to the next higher-level scheduler circuit in a scheduling domain hierarchy for redistribution to one or more other scheduling domains.

公开(公告)号：US11609791B2

公开(公告)日：2023-03-21

申请号：US15828059

申请日：2017-11-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anirudh R. Acharya ,  Michael Mantor

IPC: G06F9/50 ,  G06T1/20 ,  G06F9/52 ,  G06F9/48

Abstract: A first workload is executed in a first subset of pipelines of a processing unit. A second workload is executed in a second subset of the pipelines of the processing unit. The second workload is dependent upon the first workload. The first and second workloads are suspended and state information for the first and second workloads is stored in a first memory in response to suspending the first and second workloads. In some cases, a third workload executes in a third subset of the pipelines of the processing unit concurrently with executing the first and second workloads. In some cases, a fourth workload is executed in the first and second pipelines after suspending the first and second workloads. The first and second pipelines are resumed on the basis of the stored state information in response to completion or suspension of the fourth workload.

公开(公告)号：US20230076872A1

公开(公告)日：2023-03-09

申请号：US17985674

申请日：2022-11-11

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  James Michael O'Connor ,  Michael Mantor

IPC: G06F12/0862 ,  G06F9/52 ,  G06F8/41

Abstract: Embodiments include methods, systems and non-transitory computer-readable computer readable media including instructions for executing a prefetch kernel that includes memory accesses for prefetching data for a processing kernel into a memory, and, subsequent to executing at least a portion of the prefetch kernel, executing the processing kernel where the processing kernel includes accesses to data that is stored into the memory resulting from execution of the prefetch kernel.