公开(公告)号：US10423354B2

公开(公告)日：2019-09-24

申请号：US14863026

申请日：2015-09-23

Applicant: Advanced Micro Devices, Inc. ,  ATI TECHNOLOGIES ULC

Inventor： Philip Rogers ,  Benjamin T. Sander ,  Anthony Asaro ,  Gongxian Jeffrey Cheng

IPC: G06F3/06 ,  G06F13/28 ,  G06F12/1009

Abstract: A memory manager of a processor identifies a block of data for eviction from a first memory module to a second memory module. In response, the processor copies only those portions of the data block that have been identified as modified portions to the second memory module. The amount of data to be copied is thereby reduced, improving memory management efficiency and reducing processor power consumption.

公开(公告)号：US12032487B2

公开(公告)日：2024-07-09

申请号：US17666974

申请日：2022-02-08

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI Technologies ULC

Inventor： Benjamin T. Sander ,  Mark Fowler ,  Anthony Asaro ,  Gongxian Jeffrey Cheng ,  Michael Mantor

IPC: G06F12/10 ,  G06F12/0893 ,  G06F12/1027

CPC classification number: G06F12/1027 ,  G06F12/0893 ,  G06F2212/684

Abstract: A processor maintains an access log indicating a stream of cache misses at a cache of the processor. In response to each of at least a subset of cache misses at the cache, the processor records a corresponding entry in the access log, indicating a physical memory address of the memory access request that resulted in the corresponding miss. In addition, the processor maintains an address translation log that indicates a mapping of physical memory addresses to virtual memory addresses. In response to an address translation (e.g., a page walk) that translates a virtual address to a physical address, the processor stores a mapping of the physical address to the corresponding virtual address at an entry of the address translation log. Software executing at the processor can use the two logs for memory management.

公开(公告)号：US20170083240A1

公开(公告)日：2017-03-23

申请号：US14863026

申请日：2015-09-23

Applicant: Advanced Micro Devices, Inc. ,  ATI TECHNOLOGIES ULC

Inventor： Philip Rogers ,  Benjamin T. Sander ,  Anthony Asaro ,  Gongxian Jeffrey Cheng

IPC: G06F3/06 ,  G06F13/28 ,  G06F12/08

Abstract: A memory manager of a processor identifies a block of data for eviction from a first memory module to a second memory module. In response, the processor copies only those portions of the data block that have been identified as modified portions to the second memory module. The amount of data to be copied is thereby reduced, improving memory management efficiency and reducing processor power consumption.

公开(公告)号：US11100004B2

公开(公告)日：2021-08-24

申请号：US14747944

申请日：2015-06-23

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gongxian Jeffrey Cheng ,  Mark Fowler ,  Philip J. Rogers ,  Benjamin T. Sander ,  Anthony Asaro ,  Mike Mantor ,  Raja Koduri

IPC: G06F12/1009

Abstract: A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for different types of processing units, such as a CPU and a GPU, wherein a memory management unit uses each set of page tables to translate virtual addresses of the virtual address space to corresponding physical addresses of memory modules associated with the processor. As data is migrated between memory modules, the physical addresses in the page tables can be updated to reflect the physical location of the data for each processing unit.

公开(公告)号：US09910788B2

公开(公告)日：2018-03-06

申请号：US14861055

申请日：2015-09-22

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Philip J. Rogers ,  Benjamin T. Sander ,  Anthony Asaro

IPC: G06F12/121 ,  G06F12/0891 ,  G06F12/1081 ,  G06F13/28 ,  G06F12/12

CPC classification number: G06F12/121 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/1081 ,  G06F12/12 ,  G06F12/127 ,  G06F13/28 ,  G06F2212/656

Abstract: A processor device includes a cache and a memory storing a set of counters. Each counter of the set is associated with a corresponding block of a plurality of blocks of the cache. The processor device further includes a cache access monitor to, for each time quantum for a series of one or more time quanta, increment counter values of the set of counters based on accesses to the corresponding blocks of the cache. The processor device further includes a transfer engine to, after completion of each time quantum, transfer the counter values of the set of counters for the time quantum to a corresponding location in a system memory.

公开(公告)号：US20170083455A1

公开(公告)日：2017-03-23

申请号：US14861055

申请日：2015-09-22

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Philip J. Rogers ,  Benjamin T. Sander ,  Anthony Asaro

IPC: G06F12/12 ,  G06F12/10 ,  G06F13/28 ,  G06F12/08

CPC classification number: G06F12/121 ,  G06F12/0891 ,  G06F12/0895 ,  G06F12/1081 ,  G06F12/12 ,  G06F12/127 ,  G06F13/28 ,  G06F2212/656

Abstract: A processor device includes a cache and a memory storing a set of counters. Each counter of the set is associated with a corresponding block of a plurality of blocks of the cache. The processor device further includes a cache access monitor to, for each time quantum for a series of one or more time quanta, increment counter values of the set of counters based on accesses to the corresponding blocks of the cache. The processor device further includes a transfer engine to, after completion of each time quantum, transfer the counter values of the set of counters for the time quantum to a corresponding location in a system memory.

公开(公告)号：US20160378674A1

公开(公告)日：2016-12-29

申请号：US14747944

申请日：2015-06-23

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Gongxian Jeffrey Cheng ,  Mark Fowler ,  Philip J. Rogers ,  Benjamin T. Sander ,  Anthony Asaro ,  Mike Mantor ,  Raja Koduri

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/1072 ,  G06F12/1081 ,  G06F15/163 ,  G06F2212/1016 ,  G06F2212/151 ,  G06F2212/152 ,  G06F2212/251

Abstract: A processor uses the same virtual address space for heterogeneous processing units of the processor. The processor employs different sets of page tables for different types of processing units, such as a CPU and a GPU, wherein a memory management unit uses each set of page tables to translate virtual addresses of the virtual address space to corresponding physical addresses of memory modules associated with the processor. As data is migrated between memory modules, the physical addresses in the page tables can be updated to reflect the physical location of the data for each processing unit.

Abstract translation: 处理器对处理器的异构处理单元使用相同的虚拟地址空间。 处理器对不同类型的处理单元（例如CPU和GPU）采用不同的页表，其中存储器管理单元使用每组页表来将虚拟地址空间的虚拟地址转换为存储器模块的相应物理地址 与处理器相关联。 随着数据在内存模块之间迁移，可以更新页表中的物理地址，以反映每个处理单元的数据的物理位置。

公开(公告)号：US09501269B2

公开(公告)日：2016-11-22

申请号：US14501296

申请日：2014-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Gregory P. Rodgers ,  Benjamin T. Sander ,  Shreyas Ramalingam

IPC: G06F9/45

CPC classification number: G06F8/447

Abstract: A programming model for a processor accelerator allows accelerated functions to be called from a main program directly without a management API for the accelerator. A compiler automatically generates wrapper source code for each accelerator function called by the application source code. The wrapper code is compiled, together with the accelerator source code, to generate an object file that is linked to an object file for the main program. By automatically generating the wrapper code, a programmer can simply and directly invoke accelerator functions without the use of a complex management API. In addition, because the wrapper code for the accelerator is generated automatically, a standard compiler can be used to compile the main program, using standard linkage conventions.

Abstract translation: 处理器加速器的编程模型允许从主程序直接调用加速函数，而不需要加速器的管理API。 编译器自动为应用程序源代码调用的每个加速器函数生成包装器源代码。 包装器代码与加速器源代码一起编译，以生成链接到主程序的对象文件的对象文件。 通过自动生成包装代码，程序员可以简单直接地调用加速器功能，而无需使用复杂的管理API。 另外，由于加速器的包装代码是自动生成的，因此可以使用标准编译器来编译主程序，使用标准的链接约定。

公开(公告)号：US20130339978A1

公开(公告)日：2013-12-19

申请号：US13917484

申请日：2013-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin T. Sander

IPC: G06F9/50

CPC classification number: G06F9/505 ,  G06F9/5027 ,  G06F9/5094 ,  Y02D10/22

Abstract: A method and an apparatus for performing load balancing in a heterogeneous computing system including a plurality of processing elements are presented. A program places tasks into a queue. A task from the queue is distributed to one of the plurality of processing elements, wherein the distributing includes the one processing element sending a task request to the queue and receiving a task to be done from the queue. The task is performed by the one processing element. A result of the task is sent from the one processing element to the program. The load balancing is performed by distributing tasks from the queue to processing elements that complete the tasks faster.

Abstract translation: 提出了一种用于在包括多个处理元件的异构计算系统中执行负载平衡的方法和装置。 程序将任务放入队列。 来自队列的任务被分配到多个处理元件之一，其中分发包括一个处理元件向队列发送任务请求并从队列接收要完成的任务。 该任务由一个处理元件执行。 任务的结果从一个处理元件发送到程序。 通过将任务从队列分发到处理更快完成任务的元素来执行负载平衡。

公开(公告)号：US10467138B2

公开(公告)日：2019-11-05

申请号：US14981833

申请日：2015-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Paul Blinzer ,  Ali Ibrahim ,  Benjamin T. Sander ,  Vydhyanathan Kalyanasundharam

IPC: G06F12/0888 ,  G06F12/0815 ,  G06F12/0813 ,  H04L29/08

Abstract: A processing system includes a first socket, a second socket, and an interface between the first socket and the second socket. A first memory is associated with the first socket and a second memory is associated with the second socket. The processing system also includes a controller for the first memory. The controller is to receive a first request for a first memory transaction with the second memory and perform the first memory transaction along a path that includes the interface and bypasses at least one second cache associated with the second memory.