公开(公告)号：US20170147228A1

公开(公告)日：2017-05-25

申请号：US14952517

申请日：2015-11-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Dmitri Yudanov ,  Sergey Blagodurov ,  David A. Roberts ,  Mitesh R. Meswani ,  Nuwan Jayasena ,  Michael Ignatowski

IPC: G06F3/06

CPC classification number: G06F12/08 ,  G06F12/0811 ,  G06F12/0888 ,  G06F13/16 ,  G06F13/4022 ,  G06F15/7821 ,  G06F2212/1024

Abstract: A plurality of memory blocks are connected to a computation-enabled switch that provides data paths between the plurality of memory blocks. The computation-enabled switch performs one or more computations on data stored in one or more of the plurality of memory blocks during transfer of the data along one or more of the data paths between the plurality of memory blocks.

公开(公告)号：US20140181415A1

公开(公告)日：2014-06-26

申请号：US13723285

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel Loh ,  Nuwan Jayasena ,  James O'Connor ,  Michael Schulte ,  Michael Ignatowski

IPC: G06F12/08

CPC classification number: G06F12/0862

Abstract: Prefetching functionality on a logic die stacked with memory is described herein. A device includes a logic chip stacked with a memory chip. The logic chip includes a control block, an in-stack prefetch request handler and a memory controller. The control block receives memory requests from an external source and determines availability of the requested data in the in-stack prefetch request handler. If the data is available, the control block sends the requested data to the external source. If the data is not available, the control block obtains the requested data via the memory controller. The in-stack prefetch request handler includes a prefetch controller, a prefetcher and a prefetch buffer. The prefetcher monitors the memory requests and based on observed patterns, issues additional prefetch requests to the memory controller.

Abstract translation: 本文描述了在与存储器堆叠的逻辑管芯上的预取功能。 一种器件包括堆叠有存储器芯片的逻辑芯片。 逻辑芯片包括控制块，堆叠预取请求处理程序和存储器控制器。 控制块从外部源接收存储器请求，并确定栈内预取请求处理程序中所请求数据的可用性。 如果数据可用，则控制块将所请求的数据发送到外部源。 如果数据不可用，则控制块通过存储器控制器获得所请求的数据。 栈内预取请求处理程序包括预取控制器，预取器和预取缓冲区。 预取器监视存储器请求并基于观察到的模式，向存储器控制器发出额外的预取请求。

公开(公告)号：US12204774B2

公开(公告)日：2025-01-21

申请号：US17986623

申请日：2022-11-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexandru Dutu ,  Nuwan Jayasena ,  Yasuko Eckert ,  Niti Madan ,  Sooraj Puthoor

IPC: G06F3/06

Abstract: An apparatus includes a memory controller that includes logic to receive a first memory request having a first request type and a second memory request having a second request type. The apparatus also includes a scheduling unit that includes logic to schedule an order of the first and second memory requests for execution based upon a first parameter value and a second parameter value. The first parameter value corresponds to a utility and energy cost for the first memory request and the second parameter value corresponds to a utility and energy cost for the second memory request.

公开(公告)号：US12124531B2

公开(公告)日：2024-10-22

申请号：US18297230

申请日：2023-04-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Nuwan Jayasena ,  Allen H. Rush ,  Michael Ignatowski

IPC: G06F17/16 ,  G06F7/53 ,  G06F15/80

CPC classification number: G06F17/16 ,  G06F7/5324 ,  G06F15/8007

Abstract: A processing device including a plurality of clusters of processor cores and a method for use in the processing device is disclosed. Each processor core in a cluster of processor cores is in communication with the other processor cores in the cluster and at least one processor core of each cluster is in communication with at least a processor core of a different cluster of processor cores. Each processor core is configured to store a product of a portion of a first matrix and a first portion of a second matrix in the memory, and store a product of the portion of the first matrix and a second portion of the second matrix in the memory, where the second portion of the second matrix is received from a processor core in the cluster of processor cores.

公开(公告)号：US11868254B2

公开(公告)日：2024-01-09

申请号：US17491478

申请日：2021-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena

IPC: G06F12/08 ,  G06F12/0802

CPC classification number: G06F12/0802 ,  G06F2212/60

Abstract: An electronic device includes a cache, a memory, and a controller. The controller stores an epoch counter value in metadata for a location in the memory when a cache block evicted from the cache is stored in the location. The controller also controls how the cache block is retained in the cache based at least in part on the epoch counter value when the cache block is subsequently retrieved from the location and stored in the cache.

公开(公告)号：US11726918B2

公开(公告)日：2023-08-15

申请号：US17361145

申请日：2021-06-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Johnathan Alsop ,  Alexandru Dutu ,  Shaizeen Aga ,  Nuwan Jayasena

IPC: G06F12/0871 ,  G06F12/02 ,  G06F12/084 ,  G06F12/0846

CPC classification number: G06F12/0871 ,  G06F12/0238 ,  G06F12/084 ,  G06F12/0846

Abstract: Dynamically coalescing atomic memory operations for memory-local computing is disclosed. In an embodiment, it is determined whether a first atomic memory access and a second atomic memory access are candidates for coalescing. In response to a triggering event, the atomic memory accesses that are candidates for coalescing are coalesced in a cache prior to requesting memory-local processing by a memory-local compute unit. The atomic memory accesses may be coalesced in the same cache line or atomic memory accesses in different cache lines may be coalesced using a multicast memory-local processing command.

公开(公告)号：US11640444B2

公开(公告)日：2023-05-02

申请号：US17208526

申请日：2021-03-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Shaizeen Aga ,  Nuwan Jayasena ,  Allen H. Rush ,  Michael Ignatowski

IPC: G06F17/16 ,  G06F7/53 ,  G06F15/80

Abstract: A processing device is provided which comprises memory configured to store data and a plurality of processor cores in communication with each other via first and second hierarchical communication links. Processor cores of a first hierarchical processor core group are in communication with each other via the first hierarchical communication links and are configured to store, in the memory, a sub-portion of data of a first matrix and a sub-portion of data of a second matrix. The processor cores are also configured to determine a product of the sub-portion of data of the first matrix and the sub-portion of data of the second matrix, receive, from another processor core, another sub-portion of data of the second matrix and determine a product of the sub-portion of data of the first matrix and the other sub-portion of data of the second matrix.

公开(公告)号：US20220276795A1

公开(公告)日：2022-09-01

申请号：US17745278

申请日：2022-05-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Mahzabeen Islam ,  Shaizeen Aga ,  Nuwan Jayasena ,  Jagadish B. Kotra

IPC: G06F3/06 ,  G06F12/02

Abstract: Approaches are provided for implementing hardware-software collaborative address mapping schemes that enable mapping data elements which are accessed together in the same row of one bank or over the same rows of different banks to achieve higher performance by reducing row conflicts. Using an intra-bank frame striping policy (IBFS), corresponding subsets of data elements are interleaved into a single row of a bank. Using an intra-channel frame striping policy (ICFS), corresponding subsets of data elements are interleaved into a single channel row of a channel. A memory controller utilizes ICFS and/or IBFS to efficiently store and access data elements in memory, such as processing-in-memory (PIM) enabled memory.

公开(公告)号：US11157174B2

公开(公告)日：2021-10-26

申请号：US16659559

申请日：2019-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander D. Breslow ,  Nuwan Jayasena

IPC: G06F12/128 ,  G06F3/06 ,  G06F16/22

Abstract: A hybrid mechanism for operating on a data item in connection with an associative structure combines first-fit and K-choice. The hybrid mechanism leverages advantages of both approaches by choosing whether to insert, retrieve, delete, or modify a data item using either first-fit or K-choice. Based on the data item, a function of the data item, and/or other factors such as the load statistics of the associative structure, one of either first-fit or K-choice is used to improve operation on the associative structure across a variety of different load states of the associative structure.

公开(公告)号：US11099788B2

公开(公告)日：2021-08-24

申请号：US16658733

申请日：2019-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan Jayasena ,  Shaizeen Aga

IPC: G06F3/06 ,  H03M7/30

Abstract: An approach is provided for implementing near-memory data reduction during store operations to off-chip or off-die memory. A Near-Memory Reduction (NMR) unit provides near-memory data reduction during write operations to a specified address range. The NMR unit is configured with a range of addresses to be reduced and when a store operation specifies an address within the range of addresses, the NRM unit performs data reduction by adding the data value specified by the store operation to an accumulated reduction result. According to an embodiment, the NRM unit maintains a count of the number of updates to the accumulated reduction result that are used to determine when data reduction has been completed.