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1.发明申请公开(公告)号：US20150324131A1
公开(公告)日：2015-11-12
申请号：US14273751
申请日：2014-05-09
发明人： Gabriel Loh , Mitesh Meswani , Michael Ignatowski , Mark Nutter
IPC分类号： G06F3/06
CPC分类号： G06F3/0608 , G06F3/0605 , G06F3/0631 , G06F3/0685 , G06F12/023 , G06F2212/205 , Y02D10/13
摘要： A system for memory allocation in a multiclass memory system includes a processor coupleable to a plurality of memories sharing a unified memory address space, and a library store to store a library of software functions. The processor identifies a type of a data structure in response to a memory allocation function call to the library for allocating memory to the data structure. Using the library, the processor allocates portions of the data structure among multiple memories of the multiclass memory system based on the type of the data structure.
摘要翻译： 用于多类存储器系统中的存储器分配的系统包括可耦合到共享统一存储器地址空间的多个存储器的处理器和用于存储软件功能库的库存储。 处理器响应于对库的存储器分配功能调用来分配存储器到数据结构来识别数据结构的类型。 使用库，处理器基于数据结构的类型在多类存储器系统的多个存储器之间分配数据结构的一部分。
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2.发明申请PROCESSING DEVICE WITH INDEPENDENTLY ACTIVATABLE WORKING MEMORY BANK AND METHODS 有权具有独立可启动工作记忆体的处理装置和方法公开(公告)号：US20140181411A1
公开(公告)日：2014-06-26
申请号：US13723294
申请日：2012-12-21
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804 , G06F2212/601 , Y02D10/13
摘要： A data processing device is provided that includes an array of working memory banks and an associated processing engine. The working memory bank array is configured with at least one independently activatable memory bank. A dirty data counter (DDC) is associated with the independently activatable memory bank and is configured to reflect a count of dirty data migrated from the independently activatable memory bank upon selective deactivation of the independently activatable memory bank. The DDC is configured to selectively decrement the count of dirty data upon the reactivation of the independently activatable memory bank in connection with a transient state. In the transient state, each dirty data access by the processing engine to the reactivated memory bank is also conducted with respect to another memory bank of the array. Upon a condition that dirty data is found in the other memory bank, the count of dirty data is decremented.
摘要翻译： 提供了一种数据处理装置，其包括工作存储器组和相关处理引擎的阵列。 工作存储器阵列配置有至少一个可独立激活的存储体。 脏数据计数器（DDC）与可独立激活的存储体相关联，并且被配置为反映从可独立激活的存储体选择性地去激活时从可独立激活的存储体组迁移的脏数据的计数。 DDC被配置为在与暂时状态相关联的可独立激活的存储体的重新激活时选择性地减少脏数据的计数。 在过渡状态下，处理引擎对重新激活的存储体的每个脏数据访问也相对于阵列的另一存储体进行。 在另一个存储体中发现脏数据的情况下，脏数据的计数减少。
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公开(公告)号：US20140177347A1
公开(公告)日：2014-06-26
申请号：US13721315
申请日：2012-12-20
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C2207/2236
摘要： A method and apparatus for inter-row data transfer in memory devices is described. Data transfer from one physical location in a memory device to another is achieved without engaging the external input/output pins on the memory device. In an example method, a memory device is responsive to a row transfer (RT) command which includes a source row identifier and a target row identifier. The memory device activates a source row and storing source row data in a row buffer, latches the target row identifier into the memory device, activates a word line of a target row to prepare for a write operation, and stores the source row data from the row buffer into the target row.
摘要翻译： 描述了存储器件中行间数据传输的方法和装置。 从存储设备中的一个物理位置到另一物理位置的数据传输是在不将外部输入/输出引脚接入存储器件的情况下实现的。 在示例性方法中，存储器设备响应于包括源行标识符和目标行标识符的行传送（RT）命令。 存储器件激活源行并且将源行数据存储在行缓冲器中，将目标行标识符锁存到存储器件中，激活目标行的字线以准备写入操作，并存储源行数据 行缓冲区到目标行。
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公开(公告)号：US20240087667A1
公开(公告)日：2024-03-14
申请号：US18458052
申请日：2023-08-29
IPC分类号： G11C29/42
CPC分类号： G11C29/42
摘要： Error correction for stacked memory is described. In accordance with the described techniques, a system includes a plurality of error correction code engines to detect vulnerabilities in a stacked memory and coordinate at least one vulnerability detected for a portion of the stacked memory to at least one other portion of the stacked memory.
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公开(公告)号：US10049044B2
公开(公告)日：2018-08-14
申请号：US15181415
申请日：2016-06-14
发明人： Michael Boyer , Gabriel Loh , Nuwan Jayasena
IPC分类号： G06F12/0804 , G06F12/0806 , G06F12/0842
摘要： Proactive flush logic in a computing system is configured to perform a proactive flush operation to flush data from a first memory in a first computing device to a second memory in response to execution of a non-blocking flush instruction. Reactive flush logic in the computing system is configured to, in response to a memory request issued prior to completion of the proactive flush operation, interrupt the proactive flush operation and perform a reactive flush operation to flush requested data from the first memory to the second memory.
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公开(公告)号：US20140181415A1
公开(公告)日：2014-06-26
申请号：US13723285
申请日：2012-12-21
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： Prefetching functionality on a logic die stacked with memory is described herein. A device includes a logic chip stacked with a memory chip. The logic chip includes a control block, an in-stack prefetch request handler and a memory controller. The control block receives memory requests from an external source and determines availability of the requested data in the in-stack prefetch request handler. If the data is available, the control block sends the requested data to the external source. If the data is not available, the control block obtains the requested data via the memory controller. The in-stack prefetch request handler includes a prefetch controller, a prefetcher and a prefetch buffer. The prefetcher monitors the memory requests and based on observed patterns, issues additional prefetch requests to the memory controller.
摘要翻译： 本文描述了在与存储器堆叠的逻辑管芯上的预取功能。 一种器件包括堆叠有存储器芯片的逻辑芯片。 逻辑芯片包括控制块，堆叠预取请求处理程序和存储器控制器。 控制块从外部源接收存储器请求，并确定栈内预取请求处理程序中所请求数据的可用性。 如果数据可用，则控制块将所请求的数据发送到外部源。 如果数据不可用，则控制块通过存储器控制器获得所请求的数据。 栈内预取请求处理程序包括预取控制器，预取器和预取缓冲区。 预取器监视存储器请求并基于观察到的模式，向存储器控制器发出额外的预取请求。
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公开(公告)号：US20180039587A1
公开(公告)日：2018-02-08
申请号：US15229708
申请日：2016-08-05
发明人： Gabriel Loh
CPC分类号： G06F13/1684 , G06F13/28 , Y02D10/14
摘要： A memory network includes a plurality of memory nodes each identifiable by an ordinal number m, and a set of links divided into N subsets of links, where each subset of links is identifiable by an ordinal number n. For each subset of the plurality of N subsets of links, each link in the subset connects two memory nodes that have ordinal numbers m differing by b(n-1), where b is a positive number. Each of the memory nodes is communicatively coupled to a processor via at least two non-overlapping pathways through the plurality of links.
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公开(公告)号：US09026731B2
公开(公告)日：2015-05-05
申请号：US13725024
申请日：2012-12-21
发明人： Gabriel Loh , Jaewoong Sim
CPC分类号： G06F12/00 , G06F12/0846 , G06F12/0882 , G06F12/0888 , G06F12/0893 , Y02D10/13
摘要： A system, method and computer program product to store tag blocks in a tag buffer in order to provide early row-buffer miss detection, early page closing, and reductions in tag block transfers. A system comprises a tag buffer, a request buffer, and a memory controller. The request buffer stores a memory request having an associated tag. The memory controller compares the associated tag to a plurality of tags stored in the tag buffer and issues the memory request stored in the request buffer to either a memory cache or a main memory based on the comparison.
摘要翻译： 一种用于将标签块存储在标签缓冲器中的系统，方法和计算机程序产品，以便提供早期行缓冲器未命中检测，早期关闭和减少标签块传输。 系统包括标签缓冲器，请求缓冲器和存储器控制器。 请求缓冲器存储具有关联标签的存储器请求。 存储器控制器将相关联的标签与存储在标签缓冲器中的多个标签进行比较，并且基于该比较将存储在请求缓冲器中的存储器请求发布到存储器高速缓存或主存储器。
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公开(公告)号：US20150067264A1
公开(公告)日：2015-03-05
申请号：US14012475
申请日：2013-08-28
发明人： Yasuko Eckert , Syed Ali Jafri , Srilatha Manne , Gabriel Loh
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , Y02D10/13
摘要： In some embodiments, a method of managing cache memory includes identifying a group of cache lines in a cache memory, based on a correlation between the cache lines. The method also includes tracking evictions of cache lines in the group from the cache memory and, in response to a determination that a criterion regarding eviction of cache lines in the group from the cache memory is satisfied, selecting one or more (e.g., all) remaining cache lines in the group for eviction.
摘要翻译： 在一些实施例中，管理高速缓存存储器的方法包括基于高速缓存行之间的相关性来识别高速缓存存储器中的一组高速缓存行。 该方法还包括跟踪来自高速缓存存储器的组中的高速缓存行的移除，并且响应于确定与高速缓冲存储器中的组中的高速缓存行的逐出的标准被选择一个或多个（例如全部） 组中的剩余高速缓存行被驱逐。
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10.发明授权Processing device with independently activatable working memory bank and methods 有权具有独立可激活工作记忆库和方法的处理设备公开(公告)号：US08935472B2
公开(公告)日：2015-01-13
申请号：US13723294
申请日：2012-12-21
CPC分类号： G06F12/0891 , G06F12/0804 , G06F2212/601 , Y02D10/13
摘要： A data processing device is provided that includes an array of working memory banks and an associated processing engine. The working memory bank array is configured with at least one independently activatable memory bank. A dirty data counter (DDC) is associated with the independently activatable memory bank and is configured to reflect a count of dirty data migrated from the independently activatable memory bank upon selective deactivation of the independently activatable memory bank. The DDC is configured to selectively decrement the count of dirty data upon the reactivation of the independently activatable memory bank in connection with a transient state. In the transient state, each dirty data access by the processing engine to the reactivated memory bank is also conducted with respect to another memory bank of the array. Upon a condition that dirty data is found in the other memory bank, the count of dirty data is decremented.
摘要翻译： 提供了一种数据处理装置，其包括工作存储器组和相关处理引擎的阵列。 工作存储器阵列配置有至少一个可独立激活的存储体。 脏数据计数器（DDC）与可独立激活的存储体相关联，并且被配置为反映从可独立激活的存储体选择性地去激活时从可独立激活的存储体组迁移的脏数据的计数。 DDC被配置为在与暂时状态相关联的可独立激活的存储体的重新激活时选择性地减少脏数据的计数。 在过渡状态下，处理引擎对重新激活的存储体的每个脏数据访问也相对于阵列的另一存储体进行。 在另一个存储体中发现脏数据的情况下，脏数据的计数减少。
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