Abstract:
A display may have an array of organic light-emitting diodes that form an active area on a flexible substrate. Metal traces may extend between the active area and an inactive area of the flexible substrate. Display driver circuitry such as a display driver integrated circuit may be attached to a flexible printed circuit that is attached to the flexible substrate in the inactive area. The metal traces may extend across a bend region in the flexible substrate. The flexible substrate may be bent in the bend region. The flexible substrate may be locally thinned in the bend region. A neutral stress plane adjustment layer may cover the metal traces in the bend region. The neutral stress plane adjustment layer may include polymer layers such as an encapsulation layer, a pixel definition layer, a planarization layer, and a layer that covers a pixel definition layer and planarization layer.
Abstract:
An organic light-emitting diode display may have an array of pixels. Each pixel may have an organic light-emitting diode and thin-film transistor circuitry that controls current flow through the organic light-emitting diode. The thin-film transistor circuitry may include silicon thin-film transistors and semiconducting-oxide thin-film transistors. Double gate transistor structures may be formed in the transistors of the thin-film transistor circuitry. A double gate transistor may have a semiconductor layer sandwiched between first and second dielectric layers. The first dielectric layer may be interposed between an upper gate and the semiconductor layer and the second dielectric layer may be interposed between a lower gate and the semiconductor layer. Capacitor structures may be formed from the layers of metal used in forming the upper and lower gates and other conductive structures.
Abstract:
An organic light-emitting diode display may have an array of pixels. Each pixel may have multiple subpixels of different colors. To avoid undesired color shifts when operating the display, the display may be configured so that subpixels of different colors are not coupled to each other through parasitic capacitances. The subpixels may include red, green, and blue subpixels or subpixels of other colors. Each subpixel may include an organic light-emitting diode having an anode and a cathode. The anode of each organic light-emitting diode may be coupled to a respective storage capacitor. Capacitive coupling between subpixels can be minimized by configuring the subpixel structures of each pixel so that the storage capacitors of the subpixels do not overlap the anodes of other subpixels in the pixel. Anode and capacitor overlap with subpixel data lines may also be reduced or eliminated.
Abstract:
An electronic device may have a flexible display with portions that are bent along a bend axis. The display may have display circuitry such as an array of display pixels in an active area. Contact pads may be formed in an inactive area of the display. Signal lines may couple the display pixels to the contact pads. The signal lines may overlap the bend axis in the inactive area of the display. During fabrication, an etch stop may be formed on the display that overlaps the bend axis. The etch stop may prevent over etching of dielectric such as a buffer layer on a polymer flexible display substrate. A layer of polymer that serves as a neutral stress plane adjustment layer may be formed over the signal lines in the inactive area of the display. Upon bending, the neutral stress plane adjustment layer helps prevent stress in the signal lines.
Abstract:
An electronic device may have a flexible display with portions that can be bent. The display may include an array of display pixels in an active area. Contact pads may be formed in an inactive area of the display. Display circuitry in the active area may exhibit a given stack height, whereas display circuitry in the inactive area may exhibit a stack height that is less than the given stack height. In particular, the contact pads may be formed directly on a multi-buffer layer that sits directly on a flexible display substrate. Passivation material may be selectively formed only at the edges of the contact pad on the multi-buffer layer. The multi-buffer layer may be formed at a distance from the edge of the flexible display substrate to minimize cracking in the multi-buffer layer.
Abstract:
A method is provided for fabricating a thin-film transistor (TFT). The method includes forming a semiconductor layer over a gate insulator that covers a gate electrode, and depositing an insulator layer over the semiconductor layer, as well as etching the insulator layer to form a patterned etch-stop without losing the gate insulator. The method also includes forming a source electrode and a drain electrode over the semiconductor layer and the patterned etch-stop. The method further includes removing a portion of the semiconductor layer beyond the source electrode and the drain electrode such that a remaining portion of the semiconductor layer covers the gate insulator in a first overlapping area of the source electrode and the gate electrode and a second overlapping area of the drain electrode and gate electrode.
Abstract:
An electronic device may have a flexible display. The display may have portions that are bent along a bend axis. The display may have display circuitry such as an array of display pixels in an active area and signal lines, thin-film transistor support circuitry and other display circuitry in an inactive area of the display surrounding the active area. The display circuitry may be formed on a substrate such as a flexible polymer substrate. The flexible polymer substrate may be formed by depositing polymer on a support structure that has raised portions.The raised portions may create locally thinned regions in the flexible polymer substrate. The reduced thickness of the flexible polymer substrate in the thinned regions may help ensure that a neutral stress plane that is associated with bending the display along the bend axis is aligned with the display circuitry, thereby minimizing stress in the display circuitry.
Abstract:
A method of connecting to a first metal layer in a semiconductor flow process. Disclosed embodiments connect to the first metal layer by etching a first portion of a viahole through an etch stop layer and a gate insulation layer to reach a first metal layer, depositing a second metal layer such that the second metal layer contacts the first metal layer within the viahole, and etching a second portion of the viahole through a first passivation layer and an organic layer to reach the second metal layer.
Abstract:
A method is provided for fabricating an organic light emitting diode (OLED) display. The method includes forming a thin film transistor (TFT) substrate including a first metal layer and a second metal layer. The method also includes depositing a first passivation layer over the second metal layer, and forming a third metal layer over a channel region and a storage capacitor region. The third metal layer is configured to connect to a first portion of the second metal layer that is configured to connect to the first metal layer in a first through-hole through a gate insulator and the first passivation layer. The method further includes depositing a second passivation layer over the third metal layer, and forming an anode layer over the second passivation layer. The anode is configured to connect to a second portion of the third metal layer that is configured to connect to the second metal layer in a second through-hole of the first passivation layer and the second passivation layer.
Abstract:
Display ground plane structures may contain slits. Image pixel electrodes in the display may be arranged in rows and columns. Image pixels in the display may be controlled using gate lines that are associated with the rows and data lines that are associated with the columns. An electric field may be produced by each image pixel electrode that extends through a liquid crystal layer to an associated portion of the ground plane. The slits in the ground plane may have a slit width. Data lines may be located sufficiently below the ground plane and sufficiently out of alignment with the slits to minimize crosstalk from parasitic electric fields. A three-column inversion scheme may be used when driving data line signals into the display, so that pairs of pixels that straddle the slits are each driven with a common polarity. Gate line scanning patterns may be used that enhance display uniformity.