公开(公告)号：US10317749B2

公开(公告)日：2019-06-11

申请号：US15598902

申请日：2017-05-18

Applicant: AU OPTRONICS CORPORATION

Inventor： Chia-Chu Lin ,  Shu-Hao Huang ,  Sung-Yu Su ,  Hsiao-Wei Cheng

IPC: G09G3/36 ,  G02F1/1333 ,  G02F1/1343 ,  G02F1/1368

Abstract: A liquid crystal display panel includes first and second substrates facing each other, a liquid crystal layer between the first and second substrates, at least one pixel electrode including at least one slit and between the first substrate and the liquid crystal layer, and at least one first stripe electrode and at least one second stripe electrode between the second substrate and the liquid crystal layer. The pixel electrode and the slit extend in a first direction. The first stripe electrodes and the second stripe electrodes extend respectively in a second direction not parallel to the first direction. In a vertical projection direction from the second substrate toward the first substrate, at least a portion of the at least one pixel electrode is disposed between at least one first stripe electrode and at least one second stripe electrode, and the first and second stripe electrodes are separated from each other.

公开(公告)号：US20190035825A1

公开(公告)日：2019-01-31

申请号：US15784211

申请日：2017-10-16

Applicant: Au Optronics Corporation

Inventor： Shu-Hao Huang ,  Chin-Chuan Liu ,  Sung-Yu Su

IPC: H01L27/12 ,  H01L29/786 ,  G02F1/1368 ,  G02F1/1333 ,  G02F1/1362

Abstract: A method for fabricating an array substrate is provided. A gate insulation layer, first and second gates and a first interlayered insulation layer are formed on first and second active layers in order. A photolithography and etching process is performed by using a photo mask to form first to fourth contact holes in the gate insulation layer and the first interlayered insulation layer. First and second sources and first and second drains which are respectively connected to the first and second active layers through the first to fourth contact holes are formed. A second interlayered insulation layer is formed. Another photolithography and etching process is performed by using said photo mask to form first to third openings and a via hole in the second interlayered insulation layer, wherein along a normal direction, the third opening and the first contact hole are overlapped, the via hole and the second contact hole are overlapped, the first opening and the third contact hole are overlapped, and the second opening and the fourth contact hole are overlapped.

公开(公告)号：US20180267370A1

公开(公告)日：2018-09-20

申请号：US15918052

申请日：2018-03-12

Applicant: AU Optronics Corporation

Inventor： Kung-Ching Chu ,  Yu-min Chi ,  Chen-Feng Fan ,  Sung-Yu Su

IPC: G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  H01L27/12

CPC classification number: G02F1/134309 ,  G02F1/13624 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134318 ,  G02F2201/123 ,  H01L27/124

Abstract: A pixel structure includes first and second gate lines, at least one data line, and a pixel unit. The pixel unit has first and second display areas and includes first and second active devices, a first pixel electrode layer, a common electrode layer, and a second pixel electrode layer. The first and second active devices are electrically connected to the first and second gate lines, respectively. The first pixel electrode layer is electrically connected to the first active device. The common electrode layer is disposed above the first pixel electrode layer and includes first and second portions which are located at the first and second display areas, respectively. The second pixel electrode layer is electrically connected to the second active device, and is located above the first portion of the common electrode layer but not above the second portion, where the second pixel electrode layer has a first slit pattern and the second portion of the common electrode layer has a second slit pattern.

公开(公告)号：US10074332B2

公开(公告)日：2018-09-11

申请号：US15433069

申请日：2017-02-15

Applicant: AU Optronics Corporation

Inventor： Yu-Min Chi ,  Sung-Yu Su

IPC: G09G3/36 ,  H01L27/12

CPC classification number: G09G3/3677 ,  G09G3/3648 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2300/0465 ,  G09G2310/0251 ,  G09G2310/08 ,  H01L27/124

Abstract: A display panel includes a plurality of scanning lines, a plurality of conductive lines, a plurality of data lines, a first pixel, a second pixel, a third pixel and a fourth pixel. The data lines and the conductive lines are parallel. Each of the conductive lines is electrically coupled to one of the scanning lines, so as to transmit at least one gate pulse. The first pixel and the second pixel are located between a first data line and a first conductive line. The first pixel is electrically coupled to the first data line and a first scanning line. The second pixel is electrically coupled to the first pixel and a second scanning line. The third pixel and the fourth pixel are located between the first data line and a second conductive line. The third pixel is electrically coupled to the first data line and a third scanning line. The fourth pixel is electrically coupled to the third pixel and a fourth scanning line.

公开(公告)号：US20160370667A1

公开(公告)日：2016-12-22

申请号：US15252229

申请日：2016-08-31

Applicant: Au Optronics Corporation

Inventor： Tai-Li Hsia ,  Ya-Jung Wang ,  Sung-Yu Su

IPC: G02F1/1343 ,  H01L27/12 ,  G02F1/1368 ,  G02F1/1333 ,  G02F1/1362

CPC classification number: G02F1/134309 ,  G02F1/133345 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2201/121 ,  H01L27/124

Abstract: A liquid crystal display panel including an array substrate, an opposite substrate disposed opposite to the array substrate and liquid crystal medium between the opposite substrate and the array substrate is provided. The array substrate includes a passivation layer, an insulation layer and a first electrode. The passivation layer has a contact hole. The insulation layer is disposed on the passivation layer and has a concave at a portion overlapped with the contact hole. The first electrode is disposed on the passivation layer and the insulation layer, and has a main portion and stripe portions, wherein a gap is formed between the two adjacent stripe portions. Each stripe portion has a connection portion, at least one turning point and an extending portion. Each connection portion is directly connected to the main portion, and the contact hole is overlapped with at least one connection portion.

公开(公告)号：US11656704B2

公开(公告)日：2023-05-23

申请号：US17511610

申请日：2021-10-27

Applicant: AU Optronics Corporation

Inventor： Shu-Hao Huang ,  Sung-Yu Su

IPC: G06F3/041 ,  G06F3/044 ,  G09G3/20

CPC classification number: G06F3/0412 ,  G06F3/044 ,  G09G3/2092 ,  G09G2310/08

Abstract: A driving circuit includes a driving transistor, a capacitor, a reset circuit, a touch sensing electrode, a sensing circuit, and a read circuit. The capacitor is electrically coupled to a gate terminal of the driving transistor. The reset circuit is electrically coupled to the gate terminal of the driving transistor, and the reset circuit is configured to reset the voltage level of the gate terminal of the driving transistor. The sensing circuit is electrically coupled between the touch sensing electrode and the gate terminal of the driving transistor, and the sensing circuit is configured to transmit the voltage level of the touch sensing electrode to the gate terminal of the driving transistor. The read circuit is electrically coupled to the driving transistor, and the read circuit is configured to output a touch sensing signal according to the voltage level of the gate terminal of the driving transistor.

公开(公告)号：US20220335887A1

公开(公告)日：2022-10-20

申请号：US17724495

申请日：2022-04-20

Applicant: Au Optronics Corporation

Inventor： Ya-Jung Wang ,  Jing-Wun Jhang ,  Rong-Fu Lin ,  Nien-Chen Li ,  Hsien-Chun Wang ,  Che-Chia Chang ,  June Woo Lee ,  Hsin-Ying Lin ,  Chia-Ting Hsieh ,  Chien-Fu Huang ,  Sung-Yu Su

IPC: G09G3/32

Abstract: A pixel array is provided. The pixel array includes a plurality of red pixels, a plurality of green pixels, and a plurality of blue pixels. Each green pixel includes a light emitting diode (LED), a first transistor, a second transistor, a third transistor, and a fourth transistor. The LED receives a system low voltage. The first transistor receives a first data signal and a first scan signal. The second transistor is coupled to a second end of the first transistor and the anode of the light emitting diode. The third transistor receives a system high voltage and a first control signal, and is coupled to a first end of the second transistor. The fourth transistor is coupled to the anode of the light-emitting diode of an adjacent green pixel, a control terminal of the third transistor, and the anode of the light-emitting diode.

公开(公告)号：US11380235B2

公开(公告)日：2022-07-05

申请号：US16871066

申请日：2020-05-11

Applicant: Au Optronics Corporation

Inventor： Shu-Hao Huang ,  Sung-Yu Su

IPC: G09G3/20

Abstract: A pixel array substrate including a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixels, a first demultiplexer, a second demultiplexer, a first connecting line and a second connecting line is provided. The substrate has a display area. The first signal lines are arranged on the substrate and define a first row region and a second row region of the display area. The pixels are arranged into a first pixel row and a second pixel row which are respectively disposed in the first row region and the second row region. The first demultiplexer is disposed in the first row region and electrically connected to a part of the second signal lines. The second demultiplexer is disposed in the second row region and electrically connected to another part of the second signal lines. The first connecting line is electrically connected to the first demultiplexer. The second connecting line is electrically connected to the second demultiplexer. The electrical resistivity of the first connecting line and the second connecting line is greater than the electrically resistivity of the first signal lines and the second signal lines.

公开(公告)号：US11335248B1

公开(公告)日：2022-05-17

申请号：US17203792

申请日：2021-03-17

Applicant: AU Optronics Corporation

Inventor： Shu-Hao Huang ,  Hsien-Chun Wang ,  Sung-Yu Su

IPC: G09G3/32

Abstract: A display device includes a pixel driving circuit including a data writing unit, a light emitting unit and a compensation unit. The data writing unit includes first and second capacitors. A first terminal of the first capacitor is coupled to a first node, and a second terminal of the first capacitor is coupled to a second node. A first terminal of the second capacitor is coupled to the first node. The light emitting unit includes a first switch and a light emitting element. A control terminal of the first switch is coupled to the second node, and a first terminal of the first switch is coupled to a second terminal of the second capacitor. The compensation unit includes a second switch. The second switch is coupled to the second node and a second terminal of the first switch.

公开(公告)号：US11107842B2

公开(公告)日：2021-08-31

申请号：US16589163

申请日：2019-10-01

Applicant: Au Optronics Corporation

Inventor： Yu-Min Chi ,  Sung-Yu Su ,  Chen-Feng Fan

IPC: H01L27/12 ,  G06F3/044

Abstract: A pixel array substrate includes a substrate, a first patterned conductive layer, a pixel electrode layer, a semiconductor pattern layer, a first dielectric layer, a second patterned conductive layer, a second dielectric layer, and a common electrode layer. The first patterned conductive layer includes first and second scan lines, first and second gates, and first and second connection electrodes. The pixel electrode layer includes first and second pixel electrodes. The semiconductor pattern layer includes first and second patterns. The second patterned conductive layer includes first and second data lines, first and second sources, first and second drains, and a touch wire. The common electrode layer includes a common electrode and first and second transferring electrodes. The first transferring electrode is electrically connected to the first connection electrode and the first drain. The second transferring electrode is electrically connected to the second connection electrode and the second drain.