公开(公告)号：US20190268086A1

公开(公告)日：2019-08-29

申请号：US15903253

申请日：2018-02-23

Applicant: Advanced Micro Devices, Inc.

Inventor： John Wuu ,  Samuel Naffziger ,  Michael K. Ciraula ,  Russell Schreiber

IPC: H04J99/00 ,  H01L23/48 ,  H01L23/00

Abstract: An integrated circuit includes first and second through-silicon via (TSV) circuits and a steering logic circuit. The first TSV circuit has a first TSV and a first multiplexer for selecting between a first TSV data signal received from the first TSV and a first local data signal for transmission to a first TSV output terminal. The second TSV circuit includes a second TSV and a second multiplexer for selecting between a second TSV data signal received from the second TSV and the first local data signal for transmission to a second TSV output terminal. The steering logic circuit controls the first multiplexer to select the first local data signal and the second multiplexer to select the second TSV data signal in a first mode, and the first multiplexer to select the first TSV data signal and the second multiplexer to select the first local data signal in a second mode.

公开(公告)号：US10366734B2

公开(公告)日：2019-07-30

申请号：US15424418

申请日：2017-02-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander W. Schaefer ,  Ravi T. Jotwani ,  Samiul Haque Khan ,  David Hugh McIntyre ,  Stephen Victor Kosonocky ,  John J. Wuu ,  Russell Schreiber

IPC: G11C8/08 ,  G11C11/418 ,  G11C5/14 ,  G11C11/413 ,  G11C11/419

Abstract: A system and method for efficient power, performance and stability tradeoffs of memory accesses under a variety of conditions are described. A system management unit in a computing system interfaces with a memory and a processing unit, and uses boosting of word line voltage levels in the memory to assist write operations. The computing system supports selecting one of multiple word line boost values, each with an associated cross-over region. A cross-over region is a range of operating voltages for the memory used for determining whether to enable or disable boosting of word line voltage levels in the memory. The system management unit selects between enabling and disabling the boosting of word line voltage levels based on a target operational voltage for the memory and the cross-over region prior to updating the operating parameters of the memory to include the target operational voltage.

公开(公告)号：US10331196B2

公开(公告)日：2019-06-25

申请号：US15626847

申请日：2017-06-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber

IPC: G06F1/324 ,  H03K5/159 ,  G06F1/3296 ,  G06F1/3287

Abstract: A system and method for providing efficient clock gating capability for functional units are described. A functional unit uses a clock gating circuit for power management. A setup time of a single device propagation delay is provided for a received enable signal. When each of a clock signal, the enable signal and a delayed clock signal is asserted, an evaluate node of the clock gating circuit is discharged. When each of the clock signal and a second clock signal is asserted and the enable signal is negated, the evaluate node is left floating for a duration equal to the hold time. Afterward, the devices in a delayed onset keeper are turned on and the evaluate node has a path to the power supply. When the clock signal is negated, the evaluate node is precharged.

公开(公告)号：US09053257B2

公开(公告)日：2015-06-09

申请号：US13668705

申请日：2012-11-05

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  John Wuu ,  Keith Kasprak

IPC: H03K19/00 ,  G06F17/50 ,  G06F13/16 ,  H05K3/00 ,  G06F13/42

CPC classification number: G06F17/50 ,  G06F13/1689 ,  G06F13/4291 ,  G06F17/5045 ,  G06F2217/62 ,  H03K19/00 ,  H05K3/00

Abstract: An integrated circuit (IC) generates clock delay control signals based on its operational voltage level. The clock delay control signals are routed to corresponding clock gating logic that controls the synchronous capturing of the outputs of corresponding signal paths. The clock gating logic delays the clock signal used by the corresponding flip-flop in response to an assertion of the corresponding received clock delay control. Thus, the clock signal used to capture the outputs of certain signal paths may be delayed under certain voltage conditions. This selective clock path delay for different signal paths enables the IC to use a higher clock frequency, or more reliably latch the path outputs at a certain clock frequency, even though different signal paths may exhibit different relative path delays under different operating voltage conditions.

Abstract translation: 集成电路（IC）根据其工作电压电平产生时钟延迟控制信号。 时钟延迟控制信号被路由到对应的时钟门控逻辑，其控制相应信号路径的输出的同步捕获。 响应于对应的接收时钟延迟控制的断言，时钟门控逻辑延迟由相应触发器使用的时钟信号。 因此，用于捕获某些信号路径的输出的时钟信号可能在某些电压条件下被延迟。 即使在不同的工作电压条件下不同的信号路径可能表现出不同的相对路径延迟，不同信号路径的这种选择性时钟路径延迟使得IC能够使用更高的时钟频率，或者更可靠地锁定一定时钟频率的路径输出。