-
公开(公告)号：US5272729A
公开(公告)日：1993-12-21
申请号：US763510
申请日：1991-09-20
申请人： Roland Bechade , Frank D. Ferraiolo , Bruce Kaufmann , Ilya I. Novof , Steven F. Oakland , Kenneth Shaw , Leon Skarshinski
发明人： Roland Bechade , Frank D. Ferraiolo , Bruce Kaufmann , Ilya I. Novof , Steven F. Oakland , Kenneth Shaw , Leon Skarshinski
IPC分类号： G06F1/10 , G11C11/407 , H03K5/00 , H03K5/135 , H03K5/15 , H04J3/06 , H04L7/033 , H04L7/00 , H04L25/36 , H04L25/40
CPC分类号： H03K5/1504 , G06F1/10
摘要： A process independent digital clock signal timing network is described for generating a chip clock substantially in phase with and offset by one cycle from an input clock signal. The timing network determines the delay experienced by a clock signal passing through a predetermined internal clock circuit on the chip and pregates the internal clock circuit by an amount equivalent to the determined delay such that the chip clock signal output from the internal clock circuitry lags the external clock signal input to the semiconductor chip by one cycle. Various timing network embodiments are described and claimed.
摘要翻译： 描述了一种独立于过程的数字时钟信号定时网络，用于产生与输入时钟信号基本同相并偏移一个周期的芯片时钟。 定时网络确定通过芯片上的预定内部时钟电路的时钟信号经历的延迟，并且将内部时钟电路预先相当于所确定的延迟量，使得从内部时钟电路输出的芯片时钟信号滞后于外部 时钟信号输入到半导体芯片一个周期。 描述和要求保护各种定时网络实施例。
-
公开(公告)号：US08767531B2
公开(公告)日：2014-07-01
申请号：US13159580
申请日：2011-06-14
CPC分类号： H04L45/28 , H04L1/22 , H04L1/24 , H04L7/0025 , H04L7/0337 , H04L25/14 , H04L45/22 , H04L69/40
摘要： A communications link of multiple parallel communications lines includes at least one redundant line. In a first aspect, the lines are periodically recalibrated one at a time while the others carry functional data. If a fault is detected, the faulty line is disabled and the remaining previously calibrated lines transmit functional data. In a second aspect, impending line malfunction is detected from anomalies during calibration. In a third aspect, line malfunction is detected from receiver circuit output by determining a logical lane upon which each detected error occurs, and by mapping the logical lane to a physical line currently carrying the logical lane data.
摘要翻译： 多个并行通信线路的通信链路包括至少一个冗余线路。 在第一方面，线路一次一个地重新校准，而其他线路携带功能数据。 如果检测到故障，故障线路被禁用，其余的已校准线路传输功能数据。 在第二方面，在校准期间从异常检测到即将发生的线路故障。 在第三方面，通过确定发生每个检测到的错误的逻辑通道，并且将逻辑通道映射到当前携带逻辑车道数据的物理线路，从接收器电路输出检测线路故障。
-
43.发明申请Calibration of Multiple Parallel Data Communications Lines for High Skew Conditions 失效多个并行数据通信线路的校准用于高歪斜条件公开(公告)号：US20120106687A1
公开(公告)日：2012-05-03
申请号：US12912883
申请日：2010-10-27
申请人： John F. Bulzacchelli , Timothy O. Dickson , Frank D. Ferraiolo , Robert J. Reese , Michael B. Spear
发明人： John F. Bulzacchelli , Timothy O. Dickson , Frank D. Ferraiolo , Robert J. Reese , Michael B. Spear
IPC分类号： H04L7/00
CPC分类号： H04L25/14 , G06F2213/0038 , H04L7/0025 , H04L7/0337
摘要： A parallel data link includes a redundant line. A bank of switches permits any arbitrary line of the link to be enabled or disabled for carrying functional data, each line being dynamically calibrated in turn by disabling the line and allowing other lines to carry the functional data. The switches are located downstream of alignment mechanisms so that data input to the switches is compensated for data skew. Preferably, receiver synchronization circuitry in each line operates in a respective independent clock domain, while the switches and calibration mechanism operate in a common clock domain. Preferably, the receiver synchronization circuits provide an adjustable delay corresponding to a variable number of clock cycles to align the outputs of the receiver synchronization circuits with respect to one another, which can accommodate high data skew.
摘要翻译： 并行数据链路包括冗余线路。 一组交换机允许链路的任意任意行被启用或禁用以承载功能数据，每行通过禁用线路并允许其他线路携带功能数据依次被动态地校准。 开关位于对准机构的下游，以便数据输入到开关的数据偏移。 优选地，每行中的接收器同步电路在相应的独立时钟域中操作，而开关和校准机构在公共时钟域中操作。 优选地，接收机同步电路提供对应于可变数量的时钟周期的可调节延迟，以使接收机同步电路的输出相对于彼此对准，这可以适应高数据偏移。
-
44.发明申请Coordinating Communications Interface Activities in Data Communicating Devices Using Redundant Lines 审中-公开使用冗余线路协调数据通信设备中的通信接口活动公开(公告)号：US20120106539A1
公开(公告)日：2012-05-03
申请号：US12913064
申请日：2010-10-27
IPC分类号： H04L12/28
CPC分类号： H04J3/06 , G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： A parallel data link includes a redundant line. The redundant line permits one line to be calibrated while the others carry functional data, a switching mechanism enabling each line to be selected in turn for calibration. Control information for controlling the link, which is preferably for coordinating calibration activity, is communicated on the line selected for calibration. Preferably, the link is bi-directional, having a separate redundant line in each direction, enabling a bi-directional handshaking protocol to be used for communicating control information. Preferably, the lines selected for calibration are time-multiplexed to carry calibration patterns and control information at different time intervals.
摘要翻译： 并行数据链路包括冗余线路。 冗余线路允许一行校准，而另一条线路进行功能数据，切换机制使每条线路依次被选择进行校准。 用于控制链接的控制信息，其优选用于协调校准活动，在选择用于校准的线上传送。 优选地，链路是双向的，在每个方向上具有单独的冗余线路，使得双向握手协议能够用于传送控制信息。 优选地，选择用于校准的线被时分复用以在不同的时间间隔传送校准图案和控制信息。
-
公开(公告)号：US08001412B2
公开(公告)日：2011-08-16
申请号：US12048405
申请日：2008-03-14
IPC分类号： G06F1/04
CPC分类号： H04L25/14 , H04L7/0008 , H04L7/0037 , H04L7/005 , H04L7/044 , H04L7/046 , H04L7/10
摘要： An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambling and unscrambling operational data. The interface alignment pattern has a unique timing sequence for determining the location of a data bit's first data beat.
摘要翻译： 公开了一种用于在弹性接口上接收的用于去偏斜数据比特的接口对准模式。 接口对齐模式是“忙”，因为它具有大量的逻辑状态转换。 忙接口对准模式可用于加扰和解扰操作数据。 接口对准模式具有用于确定数据位的第一数据节拍位置的唯一定时序列。
-
公开(公告)号：US07934115B2
公开(公告)日：2011-04-26
申请号：US12332396
申请日：2008-12-11
IPC分类号： G06F1/00
CPC分类号： G06F13/4234 , G06F13/1689
摘要： A computer program product and a hub device for deriving clocks in a memory system are provided. The computer program product includes a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for facilitating a method. The method includes receiving a reference oscillator clock at the hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.
摘要翻译： 提供了一种用于在存储器系统中导出时钟的计算机程序产品和集线器设备。 计算机程序产品包括可由处理电路读取的存储介质，并且存储由处理电路执行以便于方法的指令。 该方法包括在集线器设备处接收参考振荡器时钟。 集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。 以基准时钟频率工作的基本时钟从参考振荡器时钟导出。 通过将基本时钟乘以存储器乘法器导出存储器接口时钟。 控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。 存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。
-
公开(公告)号：US20110075740A1
公开(公告)日：2011-03-31
申请号：US12568765
申请日：2009-09-29
IPC分类号： H04B3/00
CPC分类号： H04L25/0272 , Y02D30/30
摘要： An electronic system having a power efficient differential signal between a first and second electronic unit. A controller uses information, such as compliance with data transmission rate requirement and bit error rate (BER) versus a BER threshold to control power modes such that a minimal amount of power is required. Amplitude of transmission and single ended or differential transmission of data are examples of the power modes. The controller also factors in a failing phase in a differential signal in selecting a minimal power mode that satisfies the transmission rate requirement of the BER threshold.
摘要翻译： 一种在第一和第二电子单元之间具有功率有效的差分信号的电子系统。 控制器使用诸如符合数据传输速率要求和误码率（BER）与BER阈值的信息来控制功率模式，使得需要最小量的功率。 传输幅度和数据的单端或差分传输是功率模式的例子。 控制器还在选择满足BER阈值的传输速率要求的最小功率模式时，在差分信号中导致故障相位。
-
公开(公告)号：US20100005349A1
公开(公告)日：2010-01-07
申请号：US12165848
申请日：2008-07-01
IPC分类号： G06F11/00
CPC分类号： G06F11/2007 , G06F11/0724 , G06F11/076 , H04L1/20
摘要： A processing device, processing system, method, and design structure for an enhanced microprocessor interconnect with bit shadowing are provided. The processing device includes shadow selection logic to select a driver bit position as a shadowed driver value, and line drivers to transmit data for the selected driver bit position and the shadowed driver value on separate link segments of a bus. The processing device also includes shadow compare logic to compare a selected received value with a shadowed received value from the bus and identify a miscompare in response to a mismatch of the compare, and shadow counters to count a rate of the miscompare relative to a bus error rate over a period of time. A defective link segment is identified in response to the rate of the miscompare within a predefined threshold of the bus error rate.
摘要翻译： 提供了一种用于具有位阴影的增强型微处理器互连的处理装置，处理系统，方法和设计结构。 处理装置包括阴影选择逻辑以选择驱动器位位置作为阴影驱动器值，以及线驱动器，用于在总线的单独链路段上传送所选择的驱动器位位置和阴影驱动器值的数据。 处理装置还包括阴影比较逻辑，以将所选接收值与来自总线的阴影接收值进行比较，并根据比较不匹配识别错误比较，并且阴影计数器计数误差相对于总线误差的速率 率一段时间。 响应于在总线错误率的预定阈值内的错误比较的速率来识别有缺陷的链路段。
-
49.发明授权System, method and storage medium for bus calibration in a memory subsystem 失效用于内存子系统总线校准的系统，方法和存储介质公开(公告)号：US07590882B2
公开(公告)日：2009-09-15
申请号：US11780556
申请日：2007-07-20
申请人： Frank D. Ferraiolo , Kevin C. Gower
发明人： Frank D. Ferraiolo , Kevin C. Gower
CPC分类号： G06F13/4239
摘要： A cascaded interconnect system with one or more memory modules, a memory controller and a memory bus that utilizes periodic recalibration. The memory modules and the memory controller are directly interconnected by a packetized multi-transfer interface via the memory bus and provide scrambled data for use in the periodic recalibration.
摘要翻译： 具有一个或多个存储器模块的级联互连系统，存储器控制器和利用定期重新校准的存储器总线。 存储器模块和存储器控制器通过存储器总线通过分组化的多传输接口直接互连，并提供用于定期重新校准的加扰数据。
-
50.发明授权公开(公告)号：US07539800B2
公开(公告)日：2009-05-26
申请号：US10903188
申请日：2004-07-30
申请人： Timothy J. Dell , Frank D. Ferraiolo , Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
发明人： Timothy J. Dell , Frank D. Ferraiolo , Kevin C. Gower , Kevin W. Kark , Mark W. Kellogg , Warren E. Maule
CPC分类号： G06F11/201 , G06F11/104
摘要： A memory subsystem that includes segment level sparing. The memory subsystem includes a cascaded interconnect system with segment level sparing. The cascaded interconnect system includes two or more memory assemblies and a memory bus. The memory bus includes multiple segments and the memory assemblies are interconnected via the memory bus.
摘要翻译： 一个内存子系统，包括段级备份。 存储器子系统包括具有段级保护的级联互连系统。 级联互连系统包括两个或多个存储器组件和存储器总线。 存储器总线包括多个段，并且存储器组件经由存储器总线互连。
-
-
-
-
-
-
-
-
-
搜索结果
78 条记录 (耗时 0.048 秒)
