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公开(公告)号：US07934115B2
公开(公告)日：2011-04-26
申请号：US12332396
申请日：2008-12-11
IPC分类号： G06F1/00
CPC分类号： G06F13/4234 , G06F13/1689
摘要： A computer program product and a hub device for deriving clocks in a memory system are provided. The computer program product includes a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for facilitating a method. The method includes receiving a reference oscillator clock at the hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.
摘要翻译： 提供了一种用于在存储器系统中导出时钟的计算机程序产品和集线器设备。 计算机程序产品包括可由处理电路读取的存储介质，并且存储由处理电路执行以便于方法的指令。 该方法包括在集线器设备处接收参考振荡器时钟。 集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。 以基准时钟频率工作的基本时钟从参考振荡器时钟导出。 通过将基本时钟乘以存储器乘法器导出存储器接口时钟。 控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。 存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。
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公开(公告)号：US20090094476A1
公开(公告)日：2009-04-09
申请号：US12332396
申请日：2008-12-11
CPC分类号： G06F13/4234 , G06F13/1689
摘要： A computer program product and a hub device for deriving clocks in a memory system are provided. The computer program product includes a storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for facilitating a method. The method includes receiving a reference oscillator clock at the hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.
摘要翻译： 提供了一种用于在存储器系统中导出时钟的计算机程序产品和集线器设备。 计算机程序产品包括可由处理电路读取的存储介质，并且存储由处理电路执行以便于方法的指令。 该方法包括在集线器设备处接收参考振荡器时钟。 集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。 以基准时钟频率工作的基本时钟从参考振荡器时钟导出。 通过将基本时钟乘以存储器乘法器导出存储器接口时钟。 控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。 存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。
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3.发明授权公开(公告)号：US08139430B2
公开(公告)日：2012-03-20
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译： 用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。 存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。 该接口可在SBC模式和高速模式下工作。 存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。 此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。
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4.发明授权System, method and storage medium for deriving clocks in a memory system 失效用于在存储器系统中导出时钟的系统，方法和存储介质公开(公告)号：US07478259B2
公开(公告)日：2009-01-13
申请号：US11263344
申请日：2005-10-31
IPC分类号： G06F1/00
CPC分类号： G06F13/4234 , G06F13/1689
摘要： A system, method and storage medium for deriving clocks in a memory system. The method includes receiving a reference oscillator clock at a hub device. The hub device is in communication with a controller channel via a controller interface and in communication with a memory device via a memory interface. A base clock operating at a base clock frequency is derived from the reference oscillator clock. A memory interface clock is derived by multiplying the base clock by a memory multiplier. A controller interface clock is derived by multiplying the base clock by a controller multiplier. The memory interface clock is applied to the memory interface and the controller interface clock is applied to the controller interface.
摘要翻译： 一种用于在存储器系统中导出时钟的系统，方法和存储介质。 该方法包括在集线器装置处接收参考振荡器时钟。 集线器设备经由控制器接口与控制器通道通信，并且经由存储器接口与存储器设备通信。 以基准时钟频率工作的基本时钟从参考振荡器时钟导出。 通过将基本时钟乘以存储器乘法器导出存储器接口时钟。 控制器接口时钟是通过将基本时钟与控制器乘法器相乘得出的。 存储器接口时钟应用于存储器接口，控制器接口时钟应用于控制器接口。
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5.发明申请公开(公告)号：US20100005281A1
公开(公告)日：2010-01-07
申请号：US12166139
申请日：2008-07-01
申请人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
发明人： Peter L. Buchmann , Frank D. Ferraiolo , Kevin C. Gower , Robert J. Reese , Eric E. Retter , Martin L. Schmatz , Michael B. Spear , Peter M. Thomsen , Michael R. Trombley
IPC分类号： G06F9/24
CPC分类号： G06F13/4243 , Y02D10/14 , Y02D10/151
摘要： A memory buffer, memory system and method for power-on initialization and test for a cascade interconnect memory system. The memory buffer includes a bus interface to links in a high-speed channel for communicating with a memory controller via a direct connection or via a cascade interconnection through an other memory buffer. The interface is operable in a SBC mode and a high-speed mode. The memory buffer also includes a field service interface (FSI) slave for receiving FSI signals from a FSI master. In addition, the memory buffer includes logic for executing a power-on and initialization training sequence initiated by the memory controller.
摘要翻译： 用于级联互连存储器系统的上电初始化和测试的存储器缓冲器，存储器系统和方法。 存储器缓冲器包括到高速通道中的链路的总线接口，用于经由直接连接或通过其他存储器缓冲器的级联互连与存储器控制器进行通信。 该接口可在SBC模式和高速模式下工作。 存储器缓冲器还包括用于从FSI主机接收FSI信号的现场服务接口（FSI）从站。 此外，存储器缓冲器包括用于执行由存储器控制器启动的上电和初始化训练序列的逻辑。
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6.发明申请ERROR CORRECTING CODE PROTECTED QUASI-STATIC BIT COMMUNICATION ON A HIGH-SPEED BUS 失效高速总线上的错误纠正代码保护的静态位通信公开(公告)号：US20120272119A1
公开(公告)日：2012-10-25
申请号：US13535574
申请日：2012-06-28
摘要： A communication interface device, system, method, and design structure for error correcting code (ECC) protected quasi-static bit communication (SBC) on a high-speed bus are provided. The communication interface device includes high-speed sampling logic to capture high-speed data from the high-speed bus using a high-speed sampling clock and SBC sampling logic to capture SBC samples from the high-speed bus using an SBC sampling clock. The SBC sampling clock is slower than the high-speed sampling clock. The communication interface device also includes an SBC finite state machine (FSM) to detect a received SBC command in response to a static pattern persisting for a predetermined number of the SBC samples and command decoding logic to decode the received SBC command.
摘要翻译： 提供了一种用于在高速总线上进行纠错码（ECC）保护的准静态位通信（SBC）的通信接口设备，系统，方法和设计结构。 通信接口设备包括高速采样逻辑，以使用高速采样时钟和SBC采样逻辑从高速总线捕获高速数据，以使用SBC采样时钟从高速总线捕获SBC采样。 SBC采样时钟比高速采样时钟慢。 通信接口设备还包括SBC有限状态机（FSM），以响应于持续预定数量的SBC采样的静态模式和用于解码所接收的SBC命令的命令解码逻辑来检测接收到的SBC命令。
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公开(公告)号：US07512177B2
公开(公告)日：2009-03-31
申请号：US11828390
申请日：2007-07-26
IPC分类号： H04B3/46
CPC分类号： H04L25/068 , H04B3/462 , H04L1/205
摘要： Apparatuses and methods comprise a phase shifter, an adjustable capacitance configured to adjust a phase shift of said phase shifter, an arbitrary waveform generator configured to adjust the adjustable capacitance, and a pulse pattern generator coupled to the phase shifter, the phase shifter is configured to control the pulse pattern generator. In one aspect, an adjustable capacitance is at least one varactor diode. In another, a pair of varactor diodes are separated by λ/4 lines, an input and an output of the adjustable capacitance is AC-coupled, and the arbitrary waveform generator is configured to adjust the adjustable capacitance through a gaussian noise signal input to the pair of varactor diodes. A deterministic jitter generator may be coupled to the pulse pattern generator. An open-circuited stub line may be input to the pattern generator, a deterministic jitter content number adjustable varying stub line length.
摘要翻译： 装置和方法包括移相器，被配置为调整所述移相器的相移的可调电容，被配置为调节可调电容的任意波形发生器以及耦合到移相器的脉冲图形发生器，所述移相器被配置为 控制脉冲模式发生器。 在一个方面，可调电容是至少一个变容二极管。 另一方面，一对变容二极管由λ/ 4线分开，可调电容的输入和输出是交流耦合的，并且任意波形发生器被配置成通过高斯噪声信号输入到 一对变容二极管。 确定性抖动发生器可以耦合到脉冲图案发生器。 可以向模式发生器输入开路短线，确定性抖动内容数可调，可变长短线长度。
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8.发明申请STRUCTURE FOR ONE-SAMPLE-PER-BIT DECISION FEEDBACK EQUALIZER (DFE) CLOCK AND DATA RECOVERY 审中-公开一次性决策反馈均衡器（DFE）时钟和数据恢复的结构公开(公告)号：US20080240224A1
公开(公告)日：2008-10-02
申请号：US12138214
申请日：2008-06-12
申请人： JUAN A. CARBALLO , Hayden C. Cranford , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
发明人： JUAN A. CARBALLO , Hayden C. Cranford , Gareth J. Nicholls , Vernon R. Norman , Martin L. Schmatz
IPC分类号： H04L27/01
CPC分类号： H04L25/03885 , H04L25/03057 , H04L2025/03356
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design of a decision feedback equalizer (DFE) Clock-And-Data Recovery (CDR) architecture that utilizes/produces one sample-per-bit in the receiver and reduces bit-error-rate (BER) is provided. The design generally includes a receiver circuit. The receiver circuit generally includes a decision feedback equalizer (DFE) that produces one sample per bit, and means for automatically self-adjusting the DFE to enable an eye centering process by which peak energy is maintained within the receiver circuit when phase error is a minimum.
摘要翻译： 一种体现在机器可读存储介质中的设计结构，用于设计，制造和/或测试利用/产生一个每位采样的判决反馈均衡器（DFE）时钟和数据恢复（CDR）架构的设计 提供接收机并降低误码率（BER）。 该设计通常包括接收器电路。 接收器电路通常包括每位产生一个采样的判决反馈均衡器（DFE），以及用于自动自调整DFE的装置，以便当相位误差最小时能够在接收器电路内保持峰值能量的眼睛对中过程 。
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公开(公告)号：US20080133164A1
公开(公告)日：2008-06-05
申请号：US12021950
申请日：2008-01-29
CPC分类号： G01R31/31901 , G01R31/31707
摘要： A method and system for testing a high-speed circuit is disclosed. The method and system include obtaining a high-speed statistical signature of the high-speed circuit using a conventional tester. The method and system further include comparing the high-speed statistical signature of the high-speed circuit to an expected signature. Consequently, it can be determined whether the high-speed circuit functions within the desired parameters.
摘要翻译： 公开了一种用于测试高速电路的方法和系统。 该方法和系统包括使用常规测试仪获得高速电路的高速统计特征。 该方法和系统还包括将高速电路的高速统计签名与预期签名进行比较。 因此，可以确定高速电路是否在期望的参数内起作用。
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公开(公告)号：US07317777B2
公开(公告)日：2008-01-08
申请号：US10265759
申请日：2002-10-07
IPC分类号： H04L25/00
CPC分类号： H03L7/091 , H04L7/0337
摘要： A system and method for tracking/adapting phase or frequency changes in an incoming serial data stream that may contain significant amounts of noise and/or jitter and may contain relatively long periods of successive univalue data bits. The method includes digitally sampling a received data stream at predefined intervals to produce a data set; estimating when logic transitions occur in the data set; detecting a timing trend represented by the estimated logic transitions; and adjusting a frequency of the first clock so that the timing trend averages approximately zero over a plurality of logic transitions.
摘要翻译： 用于跟踪/调整可能包含大量噪声和/或抖动的输入串行数据流中的相位或频率变化的系统和方法，并且可以包含相对较长的连续的单值数据位。 该方法包括以预定的间隔对接收的数据流进行数字采样以产生数据集; 在数据集中发生逻辑转换时估计; 检测由所估计的逻辑转换表示的定时趋势; 以及调整所述第一时钟的频率，使得所述时序趋势在多个逻辑转换中平均为零。
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