公开(公告)号：US12000870B2

公开(公告)日：2024-06-04

申请号：US17931197

申请日：2022-09-12

Applicant: Allegro MicroSystems, LLC

Inventor： Samridh Jaiswal ,  Paolo Campiglio ,  Sundar Chetlur ,  Maxim Klebanov ,  Yen Ting Liu

IPC: G01R33/09 ,  G01R15/20 ,  G01R19/00

CPC classification number: G01R15/205 ,  G01R19/0092

Abstract: In one aspect, a sensor includes a first metal layer portion and a second metal layer portion separated by an insulator material; a conductive material layer in electrical contact with the first metal layer portion and the second metal layer portion; and a tunnel magnetoresistance (TMR) element positioned on and in electrical contact with the conductive material layer. A first current is configured to flow from the first metal layer portion, through the conductive material layer, to the second metal layer portion, and a second current is configured to flow from the first metal layer portion, through the conductive material layer, through the TMR element, and exiting through a top of the TMR element.

公开(公告)号：US11967650B2

公开(公告)日：2024-04-23

申请号：US17662101

申请日：2022-05-05

Applicant: Allegro MicroSystems, LLC

Inventor： Sagar Saxena ,  Washington Lamar ,  Maxim Klebanov ,  Chung C. Kuo ,  Sebastian Courtney ,  Sundar Chetlur

IPC: H01L29/87 ,  H01L29/06

CPC classification number: H01L29/87 ,  H01L29/0684

Abstract: In one aspect, a diode includes a substrate having a first type dopant; a buried layer having a second type dopant and formed within the substrate; an epitaxial layer having the second type dopant and formed above the buried layer; and a plurality of regions having the first type dopant within the epitaxial layer. The plurality of regions includes a first region, a second region, and a third region. The diode also includes a base well having the first type dopant and located within the epitaxial layer and in contact with the third and fourth regions. In a reverse-bias mode, the diode is an electrostatic discharge (ESD) clamp and forms parasitic transistors comprising a first bipolar junction transistor (BJT), a second BJT and a third BJT.

公开(公告)号：US11782105B2

公开(公告)日：2023-10-10

申请号：US17648151

申请日：2022-01-17

Applicant: Allegro MicroSystems, LLC

Inventor： Maxim Klebanov ,  Yen Ting Liu ,  Paolo Campiglio ,  Sundar Chetlur ,  Harianto Wong

IPC: G01R33/09 ,  G01R3/00

CPC classification number: G01R33/093 ,  G01R3/00 ,  G01R33/098

Abstract: In one aspect, a method includes forming a coil in a coil layer, performing planarization on the coil layer, and depositing a magnetoresistance (MR) element on the planarized coil layer. No dielectric material is between the planarized coil layer and the MR element. In another aspect, a magnetic field sensor includes a substrate, a planarized coil layer comprising a coil on the substrate, a magnetoresistance (MR) element in contact with the planarized coil layer, and a capping layer deposited over the MR element and the planarized coil layer. No dielectric material is between the planarized coil layer and the MR element.

公开(公告)号：US11719771B1

公开(公告)日：2023-08-08

申请号：US17805054

申请日：2022-06-02

Applicant: Allegro MicroSystems, LLC

Inventor： Paolo Campiglio ,  Samridh Jaiswal ,  Yen Ting Liu ,  Maxim Klebanov ,  Sundar Chetlur

IPC: G01R33/09 ,  H10N50/80 ,  H10N50/85

CPC classification number: G01R33/091 ,  H10N50/80 ,  H10N50/85 ,  G01R33/093 ,  G01R33/096 ,  G01R33/098

Abstract: Methods and apparatus for a magnetoresistive (MR) sensor including a seed layer having a CoFe layer for canceling hysteresis in the MR sensor. The MR stackup can include a free layer and a reference layer. The seed layer having CoFe provides a desired texturing of the stackup to cancel hysteresis effects.

公开(公告)号：US11515246B2

公开(公告)日：2022-11-29

申请号：US17067178

申请日：2020-10-09

Applicant: Allegro MicroSystems, LLC

Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Cory Voisine ,  Kenneth Snowdon ,  Hsuan-Jung Wu

IPC: H01L23/522 ,  H01L21/8234

Abstract: An apparatus, comprising: a substrate; a coupling capacitor that is formed over the substrate; and an isolator that is formed between the substrate and the coupling capacitor, the isolator including: (a) an MP-well layer, (b) a first well layer, (c) an epi tub layer that is nested in the MP-well layer and the first well layer, and (d) a second well layer that is nested in the epi tub layer.

公开(公告)号：US20220077382A1

公开(公告)日：2022-03-10

申请号：US17014129

申请日：2020-09-08

Applicant: Allegro MicroSystems, LLC

Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Paolo Campiglio ,  Yen Ting Liu

IPC: H01L43/02 ,  H01L27/22 ,  G01R33/09 ,  H01L43/08 ,  H01L43/12

Abstract: In one aspect, an integrated circuit includes a first conductive layer and a magnetoresistance element (MRE) disposed over and coupled to the first layer through first vias. The MRE is magnetized to produce a first magnetic orientation. The first layer is disposed over and coupled to a second conductive layer in the circuit through second vias. The circuit also includes a metal filler disposed proximate to the MRE. The metal filler is positioned over and coupled to the second layer through third vias. The circuit also includes a thermal dissipation path resulting from a physical input applied to the first MRE. The thermal dissipation path extends through the first through third vias, the first and second layers, an integrated circuit interconnection, and the metal filler.

公开(公告)号：US10943976B2

公开(公告)日：2021-03-09

申请号：US16537725

申请日：2019-08-12

Applicant: Allegro MicroSystems, LLC

Inventor： Sundar Chetlur ,  Maxim Klebanov ,  Washington Lamar

IPC: H01L29/08 ,  H01L29/423 ,  H01L27/088 ,  H01L29/78 ,  H01L29/51 ,  H01L29/06 ,  H01L27/02 ,  H01L21/8234

Abstract: A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.

公开(公告)号：US20200266337A1

公开(公告)日：2020-08-20

申请号：US16280199

申请日：2019-02-20

Applicant: Allegro MicroSystems, LLC

Inventor： Yen Ting Liu ,  Maxim Klebanov ,  Bryan Cadugan ,  Sundar Chetlur ,  Harianto Wong

IPC: H01L43/12

Abstract: A manufacturing method results in a magnetoresistance element having conductive contacts disposed between the magnetoresistance element and a semiconductor substrate.

公开(公告)号：US10352969B2

公开(公告)日：2019-07-16

申请号：US15363285

申请日：2016-11-29

Applicant: Allegro MicroSystems, LLC

Inventor： Shaun D. Milano ,  Bryan Cadugan ,  Michael C. Doogue ,  Alexander Latham ,  William P. Taylor ,  Harianto Wong ,  Sundar Chetlur

IPC: G01R15/14 ,  G01R19/00 ,  G01R15/20

Abstract: Systems and methods described herein are directed towards integrating a shield layer into a current sensor to shield a magnetic field sensing element and associated circuitry in the current sensor from electrical, voltage, or electrical transient noise. In an embodiment, a shield layer may be disposed along at least one surface of a die supporting a magnetic field sensing element. The shield layer may be disposed in various arrangements to shunt noise caused by a parasitic coupling between the magnetic field sensing element and the current carrying conductor away from the magnetic field sensing element.