公开(公告)号：US11163719B2

公开(公告)日：2021-11-02

申请号：US16661876

申请日：2019-10-23

Applicant: Amazon Technologies, Inc.

Inventor： Erez Izenberg ,  Leah Shalev ,  Georgy Machulsky ,  Nafea Bshara

IPC: G06F15/173 ,  H04L29/08 ,  G06F3/06

Abstract: A technique for remote direct memory access (RDMA) may include receiving a packet that was sent over a network, and determining the packet has metadata indicative of acceleration. The technique may also include selecting a queue having minimal storage stages to process the packet, and writing the data of the packet to an application memory using the datapath associated with the queue. Amended metadata can be generated to indicate that the data has been written to the application memory, and the amended metadata can be stored in a software accessible buffer.

公开(公告)号：US10863009B2

公开(公告)日：2020-12-08

申请号：US16435266

申请日：2019-06-07

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Naaman ,  Erez Izenberg ,  Nafea Bshara

IPC: H04L29/06 ,  G06F17/30 ,  H04L12/861 ,  H04L12/931 ,  H04L12/721 ,  H04L12/741 ,  H04L12/851 ,  H04L12/801 ,  H04L1/00 ,  G06F9/30 ,  G06F13/38 ,  H04L12/803

Abstract: A system, comprising: a configurable parser that comprises one or more configurable parsing engines, wherein the configurable parser is arranged to receive a packet and to extract from the packet headers associated with a set of protocols that comprises at least one protocol; a packet type detection unit that is arranged to determine a type of the packet in response to the set of protocols; and a configurable data integrity unit that comprises a configuration unit and at least one configurable data integrity engine; wherein the configuration unit is arranged to configure the at least one configurable data integrity engine according to the set of protocols; and wherein the at least one configurable data integrity engine is arranged to perform data integrity processing of the packet to provide at least one data integrity result.

公开(公告)号：US20200257454A1

公开(公告)日：2020-08-13

申请号：US16863700

申请日：2020-04-30

Applicant: Amazon Technologies, Inc.

Inventor： Mark Bradley Davis ,  Erez Izenberg ,  Robert Michael Johnson ,  Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Nafea Bshara ,  Christopher Joseph Pettey

IPC: G06F3/06 ,  G06F15/78 ,  G06F21/51 ,  G06F13/28 ,  G11C7/10

Abstract: Methods and apparatus are disclosed for securely erasing partitions of reconfigurable logic devices such as FPGAs in a multi-tenant server environment. In one example, a method of securely erasing an FPGA includes identifying one partition of previously-programmed resources in the FPGA, erasing the identified partition by storing new values in memory or storage elements of the identified partition, and storing new values in memory or storage elements of additional external resources electrically connected to the integrated circuit and associated with the identified partition. Thus, other partitions and subsequent users of the identified partition are prevented from accessing the securely erased data. A configuration circuit, accessible by a host computer via DMA, can be programmed into the FPGA reconfigurable logic for performing the disclosed erasing operations.

公开(公告)号：US10727966B1

公开(公告)日：2020-07-28

申请号：US15691503

申请日：2017-08-30

Applicant: Amazon Technologies, Inc.

Inventor： Erez Izenberg ,  Nafea Bshara

IPC: H04J3/06

Abstract: In various implementations, provided are techniques for distributing network time across a network using multiple grand masters (e.g., master time keepers). These techniques include having multiple grand masters simultaneously providing time to the network. Simultaneous means that all the grand masters are active at the same time, and none are designated as backups. In various implementations, the nodes in the network can simultaneously synchronize to network times provided by more than grand masters so that the nodes can obtain more than one network time. Using these multiple network times, nodes configured as clients can determine one network time. The client devices can then use the single network time in applications that require a time.

公开(公告)号：US10705995B2

公开(公告)日：2020-07-07

申请号：US16361007

申请日：2019-03-21

Applicant: Amazon Technologies, Inc.

Inventor： Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Christopher Joseph Pettey ,  Nafea Bshara ,  Erez Izenberg

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/40 ,  G06F9/50

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

公开(公告)号：US10594476B1

公开(公告)日：2020-03-17

申请号：US15966127

申请日：2018-04-30

Applicant: AMAZON TECHNOLOGIES, INC.

Inventor： Ron Diamant ,  Nafea Bshara ,  Erez Izenberg

IPC: H04L9/06 ,  H04L9/08

Abstract: A hardware cipher module to cipher a packet. The cipher module includes a key scheduling engine and a ciphering engine. The key scheduling engine is configured to receive a compact key and iteratively generate a set of round keys, including a first round key, based on the compact key and determine, based upon a cipher mode indication and a type of ciphering whether to generate a key-scheduling-done indication after the first round key is generated and before all of the set of round keys are generated or to generate the key-scheduling-done indication after all of the set of round keys is generated. The ciphering engine is configured to begin to cipher the packet with one of the set of round keys as a result of receiving the key schedule done indication.

公开(公告)号：US20200057747A1

公开(公告)日：2020-02-20

申请号：US16661876

申请日：2019-10-23

Applicant: Amazon Technologies, Inc.

Inventor： Erez Izenberg ,  Leah Shalev ,  Georgy Machulsky ,  Nafea Bshara

IPC: G06F15/173 ,  G06F3/06 ,  H04L29/08

Abstract: A technique for remote direct memory access (RDMA) may include receiving a packet that was sent over a network, and determining the packet has metadata indicative of acceleration. The technique may also include selecting a queue having minimal storage stages to process the packet, and writing the data of the packet to an application memory using the datapath associated with the queue. Amended metadata can be generated to indicate that the data has been written to the application memory, and the amended metadata can be stored in a software accessible buffer.

公开(公告)号：US20190215021A1

公开(公告)日：2019-07-11

申请号：US16241275

申请日：2019-01-07

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Frishman ,  Erez Izenberg ,  Guy Nakibly

IPC: H03M13/00 ,  G06F12/0813 ,  H03M13/09 ,  H04L29/06 ,  G06F11/10 ,  G06F12/12

Abstract: Systems and methods in accordance with various embodiments of the present disclosure provide approaches for mapping entries to a cache using a function, such as cyclic redundancy check (CRC). The function can calculate a colored cache index based on a main memory address. The function may cause consecutive address cache indexes to be spread throughout the cache according to the indexes calculated by the function. In some embodiments, each data context may be associated with a different function, enabling different types of packets to be processed while sharing the same cache, reducing evictions of other data contexts and improving performance. Various embodiments can identify a type of packet as the packet is received, and lookup a mapping function based on the type of packet. The function can then be used to lookup the corresponding data context for the packet from the cache, for processing the packet.

公开(公告)号：US20170270064A1

公开(公告)日：2017-09-21

申请号：US15616832

申请日：2017-06-07

Applicant: Amazon Technologies, Inc.

Inventor： Said Bshara ,  Erez Izenberg ,  Yaniv Shapira ,  Nafea Bshara

IPC: G06F13/24 ,  G06F9/48

CPC classification number: G06F13/24 ,  G06F9/4812 ,  G06F2213/2408

Abstract: An interrupt request generating process can include determining a first interrupt triggering event has occurred after a predetermined period of time in which no interrupt triggering event occurred. In response to determining that the first interrupt triggering event has occurred, the interrupt request generating process may generate a first interrupt request without adding an intentional delay, and initiating a timer configured to expire after a predetermined time interval. When a second interrupt triggering event is determined to have occurred before the timer expires, a second interrupt request is delayed from being generated until the timer expires.

公开(公告)号：US11989154B2

公开(公告)日：2024-05-21

申请号：US17451753

申请日：2021-10-21

Applicant: Amazon Technologies, Inc.

Inventor： Erez Izenberg ,  Leah Shalev ,  Georgy Machulsky ,  Nafea Bshara

IPC: G06F15/173 ,  G06F3/06 ,  H04L67/1097

CPC classification number: G06F15/17331 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/067 ,  H04L67/1097

Abstract: A technique for remote direct memory access (RDMA) may include receiving a packet that was sent over a network, and determining the packet has metadata used for queue selection. The technique may also include selecting a queue based on the metadata, and writing the data of the packet to an application memory using the datapath associated with the selected queue. Amended metadata can be generated to indicate that the data has been written to the application memory, and the amended metadata can be stored in a software accessible buffer.