公开(公告)号：US12056067B1

公开(公告)日：2024-08-06

申请号：US17039125

申请日：2020-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Jonathan Cohen ,  Said Bshara ,  Leah Shalev ,  Erez Izenberg ,  Rotem Shaanan

IPC: G06F13/16 ,  G06F9/30 ,  G06F13/28 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F13/1673 ,  G06F9/30101 ,  G06F13/161 ,  G06F13/1642 ,  G06F13/28 ,  G06F15/17375 ,  G06F15/7807

Abstract: Systems and methods are provided to reduce the latency in accessing an input/output (I/O) hardware register by software executing on a central processing unit (CPU). The hardware register is located in a controller coupled to the CPU via an I/O bus. The CPU software can send a command to the controller for execution. The controller can execute the command and update the hardware register to indicate that the command has been executed. The controller can write contents of the hardware register to a specified address in a CPU memory that is assigned by the CPU software. The CPU software can read the specified address to determine that the command has been executed instead of reading the hardware register on the I/O bus.

公开(公告)号：US20240134811A1

公开(公告)日：2024-04-25

申请号：US18383833

申请日：2023-10-24

Applicant: Amazon Technologies, Inc.

Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42 ,  G06F15/78

CPC classification number: G06F13/4068 ,  G06F9/44505 ,  G06F13/4282 ,  G06F15/7867 ,  G06F15/7871

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

公开(公告)号：US11870761B1

公开(公告)日：2024-01-09

申请号：US18046904

申请日：2022-10-14

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Nafea Bshara ,  Leah Shalev ,  Erez Izenberg

IPC: H04L9/40 ,  H04L9/32 ,  H04L9/08 ,  G09C1/00 ,  H04L9/14

CPC classification number: H04L63/0428 ,  G09C1/00 ,  H04L9/0877 ,  H04L9/14 ,  H04L9/3234 ,  H04L9/3247 ,  H04L2209/12 ,  H04L2209/24

Abstract: An integrated circuit device includes a packet type detection circuit, a security circuitry, and a configuration circuit. The packet type detection circuit is operable to determine a packet type of a packet based on header portions of the packet. The security circuit is operable to perform security processing of the packet according to a set of security parameters. The configuration circuit operable to determine the set of security parameters based on the packet type of the packet, an identifier associated with the packet, and an index associated with the packet, and provide the set of security parameters to the security circuit.

公开(公告)号：US20230007106A1

公开(公告)日：2023-01-05

申请号：US17930696

申请日：2022-09-08

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Naaman ,  Erez Izenberg ,  Nafea Bshara

IPC: H04L69/22 ,  H04L49/90 ,  H04L49/60 ,  H04L45/00 ,  H04L45/74 ,  H04L47/2425 ,  H04L47/10 ,  G06F16/182 ,  G06F16/245 ,  G06F16/00 ,  G06F16/13 ,  G06F16/90 ,  G06F16/25 ,  G06F16/2458 ,  G06F16/903 ,  H04L69/00 ,  H04L69/12 ,  H04L69/16

Abstract: A packet processing technique can include receiving a packet, and parsing the packet based on a protocol field to generate a parse result vector. The parse result vector is used to select between forwarding the packet to a virtual machine executing on a host processing integrated circuit, forwarding the packet to a physical media access controller, multicasting the packet to multiple virtual machines executing on the host processing integrated circuit, and sending the packet to a hypervisor.

公开(公告)号：US20220035766A1

公开(公告)日：2022-02-03

申请号：US17451753

申请日：2021-10-21

Applicant: Amazon Technologies, Inc.

Inventor： Erez Izenberg ,  Leah Shalev ,  Georgy Machulsky ,  Nafea Bshara

IPC: G06F15/173 ,  H04L29/08 ,  G06F3/06

Abstract: A technique for remote direct memory access (RDMA) may include receiving a packet that was sent over a network, and determining the packet has metadata used for queue selection. The technique may also include selecting a queue based on the metadata, and writing the data of the packet to an application memory using the datapath associated with the selected queue. Amended metadata can be generated to indicate that the data has been written to the application memory, and the amended metadata can be stored in a software accessible buffer.

公开(公告)号：US11157452B2

公开(公告)日：2021-10-26

申请号：US15590898

申请日：2017-05-09

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Leah Shalev ,  Erez Izenberg ,  Georgy Machulsky ,  Ron Diamant

IPC: G06F16/174 ,  G06F16/27 ,  G06F16/901

Abstract: A method for in-band de-duplication, the method may include receiving by a hardware accelerator, a received packet of a first sequence of packets that conveys a first data chunk; applying a data chunk hash calculation process on the received packet while taking into account a hash calculation result obtained when applying the data chunk hash calculation process on a last packet of the first sequence that preceded the received packet; wherein the calculating of the first data chunk hash value is initiated before a completion of a reception of the entire first data chunk by the hardware accelerator.

公开(公告)号：US11121915B2

公开(公告)日：2021-09-14

申请号：US16120134

申请日：2018-08-31

Applicant: Amazon Technologies, Inc.

Inventor： Erez Izenberg ,  Nafea Bshara ,  Christopher Pettey ,  Curtis Karl Ohrt

IPC: H04L12/24 ,  G06F15/78 ,  G06F9/50 ,  G06F9/455

Abstract: A resource manager of a virtualized computing service indicates to a client that FPGA-enabled compute instances are supported at the service. From a set of virtualization hosts of the service, a particular host from which an FPGA is accessible is selected for the client based on an indication of computation objectives of the client. Configuration operations are performed to prepare the host for the application, and an FPGA-enabled compute instance is launched at the host for the client.

公开(公告)号：US10509764B1

公开(公告)日：2019-12-17

申请号：US15164601

申请日：2016-05-25

Applicant: Amazon Technologies, Inc.

Inventor： Erez Izenberg ,  Leah Shalev ,  Nafea Bshara ,  Guy Nakibly ,  Georgy Machulsky

IPC: G06F15/167 ,  H04L29/06 ,  G06F16/22

Abstract: Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network according to a number of different RDMA protocols. In one example, a method includes receiving remote direct memory access (RDMA) packets via a network adapter, deriving a protocol index identifying an RDMA protocol used to encode data for an RDMA transaction associated with the RDMA packets, applying the protocol index to a generate RDMA commands from header information in at least one of the received RDMA packets, and performing an RDMA operation using the RDMA commands.

公开(公告)号：US20190364136A1

公开(公告)日：2019-11-28

申请号：US16435266

申请日：2019-06-07

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Naaman ,  Erez Izenberg ,  Nafea Bshara

IPC: H04L29/06 ,  H04L12/851 ,  H04L12/801

Abstract: A system, comprising: a configurable parser that comprises one or more configurable parsing engines, wherein the configurable parser is arranged to receive a packet and to extract from the packet headers associated with a set of protocols that comprises at least one protocol; a packet type detection unit that is arranged to determine a type of the packet in response to the set of protocols; and a configurable data integrity unit that comprises a configuration unit and at least one configurable data integrity engine; wherein the configuration unit is arranged to configure the at least one configurable data integrity engine according to the set of protocols; and wherein the at least one configurable data integrity engine is arranged to perform data integrity processing of the packet to provide at least one data integrity result

公开(公告)号：US10459875B2

公开(公告)日：2019-10-29

申请号：US15360853

申请日：2016-11-23

Applicant: Amazon Technologies, Inc.

Inventor： Erez Izenberg ,  Leah Shalev ,  Georgy Machulsky ,  Nafea Bshara

IPC: H04L29/08 ,  G06F15/173 ,  G06F3/06

Abstract: According to an embodiment of the invention there may be provided a method for hybrid remote direct memory access (RDMA), the method may include: (i) receiving, by a first computer, a packet that was sent over a network from a second computer; wherein the packet may include data and metadata; (ii) determining, in response to the metadata, whether the data should be (a) directly written to a first application memory of the first computer by a first hardware accelerator of the first computer; or (b) indirectly written to the first application memory; (iii) indirectly writing the data to the first application memory if it determined that the data should be indirectly written to the first application memory; (iv) if it determined that the data should be directly written to the first application memory then: (iv.a) directly writing, by the first hardware accelerator the data to the first application memory without writing the data to any buffer of the operating system; and (iv.b) informing a first RDMA software module, by the first hardware accelerator, that the data was directly written to the first application memory; and (v) notifying, by the first RDMA software module, a second computer about a completion of an RDMA transaction during which the data was directly written to the first application memory.