公开(公告)号：US09773663B2

公开(公告)日：2017-09-26

申请号：US15230218

申请日：2016-08-05

Applicant: Applied Materials, Inc. ,  The Regents of the University of California

Inventor： Jessica S. Kachian ,  Naomi Yoshida ,  Mei Chang ,  Mary Edmonds ,  Andrew C. Kummel ,  Sang Wook Park ,  Hyunwoong Kim

IPC: H01L21/02

CPC classification number: H01L21/0228 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/022 ,  H01L21/02205 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02299 ,  H01L21/02301 ,  H01L21/02304

Abstract: Embodiments described herein provide a self-limiting and saturating Si—Ox bilayer process which does not require the use of a plasma or catalyst and that does not lead to undesirable substrate oxidation. Methods of the disclosure do not produce SiO2, but instead produce a saturated Si—Ox film with —OH termination to make substrate surfaces highly reactive towards metal ALD precursors to seed high nucleation and growth of gate oxide ALD materials.

公开(公告)号：US09748354B2

公开(公告)日：2017-08-29

申请号：US15043883

申请日：2016-02-15

Applicant: APPLIED MATERIALS, INC.

Inventor： Wei V. Tang ,  Paul F. Ma ,  Steven C. H. Hung ,  Michael Chudzik ,  Siddarth Krishnan ,  Wenyu Zhang ,  Seshadri Ganguli ,  Naomi Yoshida ,  Lin Dong ,  Yixiong Yang ,  Liqi Wu ,  Shih Chung Chen

IPC: H01L29/76 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L29/51 ,  H01L29/49

CPC classification number: H01L29/66446 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78603 ,  H01L29/78681

Abstract: Semiconductor devices incorporating multi-threshold voltage structures and methods of forming such semiconductor devices are provided herein. In some embodiments of the present disclosure, a semiconductor device having a multi-threshold voltage structure includes: a substrate; a gate dielectric layer atop the substrate, wherein the gate dielectric layer comprises an interface layer and a high-k dielectric layer atop the interface layer; a lanthanum nitride layer deposited atop the high-k dielectric layer; an interface of the interface layer and the high-k dielectric layer comprising lanthanum species from the lanthanum nitride layer; and a gate electrode layer atop the lanthanum nitride layer.

公开(公告)号：US09673277B2

公开(公告)日：2017-06-06

申请号：US14885521

申请日：2015-10-16

Applicant: APPLIED MATERIALS, INC.

Inventor： Adam Brand ,  Bingxi Sun Wood ,  Naomi Yoshida ,  Lin Dong ,  Shiyu Sun ,  Chi-Nung Ni ,  Yihwan Kim

IPC: H01L29/06 ,  H01L29/20 ,  H01L29/66 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L29/0673 ,  H01L21/30612 ,  H01L21/76224 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78696

Abstract: A method of forming a semiconductor device includes: forming a superlattice structure atop the top surface of a substrate, wherein the superlattice structure comprises a plurality of first layers and a corresponding plurality of second layers alternatingly arranged in a plurality of stacked pairs; forming a lateral etch stop layer by epitaxial deposition of a material of the first layer or the second layer of the superlattice structure atop a sidewall of the superlattice structure, or by selectively oxidizing edges of the first layers and second layers of the superlattice structure; subsequently forming a source region adjacent a first end of the superlattice structure and a drain region adjacent a second opposing end of the superlattice structure; and selectively etching the superlattice structure to remove each of the first layers or each of the second layers to form a plurality of voids in the superlattice structure.

公开(公告)号：US09355820B2

公开(公告)日：2016-05-31

申请号：US14484397

申请日：2014-09-12

Applicant: APPLIED MATERIALS, INC.

Inventor： Wei Liu ,  Naomi Yoshida ,  Mandar Balasaheb Pandit

IPC: H01L21/302 ,  H01L21/461 ,  B44C1/22 ,  C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01J37/32 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/8238

CPC classification number: H01J37/321 ,  H01L21/3065 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823828

Abstract: Embodiments of methods for removing carbon-containing films are provided herein. In some embodiments, a method for removing a carbon-containing layer includes providing an ammonia containing process gas to a process chamber having a substrate with a silicon oxide layer disposed atop the substrate and a carbon-containing layer disposed atop the silicon oxide layer disposed in the process chamber; providing RF power to the process chamber to ignite the ammonia containing process gas to form a plasma; and exposing the substrate to NH and/or NH2 radicals and hydrogen radicals formed in the plasma to remove the carbon-containing layer.

Abstract translation: 本文提供了用于除去含碳膜的方法的实施方案。 在一些实施方案中，用于除去含碳层的方法包括向具有衬底的处理室提供含氨工艺气体，所述衬底具有设置在衬底顶部的氧化硅层和设置在设置在衬底上的氧化硅层顶部的含碳层 处理室; 向处理室提供RF功率以点燃含氨工艺气体以形成等离子体; 并将衬底暴露于NH和/或NH 2基团和在等离子体中形成的氢原子以除去含碳层。

公开(公告)号：US20160056033A1

公开(公告)日：2016-02-25

申请号：US14830131

申请日：2015-08-19

Applicant: The Regents of the University of California ,  GLOBALFOUNDRIES, Inc. ,  Applied Materials, Inc.

Inventor： Kasra Sardashti ,  Tobin Kaufman-Osborn ,  Tyler Kent ,  Andrew Kummel ,  Shariq Siddiqui ,  Bhagawan Sahu ,  Adam Brand ,  Naomi Yoshida

IPC: H01L21/02

CPC classification number: H01L21/0228 ,  H01L21/0206 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02301 ,  H01L21/02315 ,  H01L21/306 ,  H01L29/66181 ,  H01L29/94

Abstract: Surface pretreatment of SiGe or Ge surfaces prior to gate oxide deposition cleans the SiGe or Ge surface to provide a hydrogen terminated surface or a sulfur passivated (or S—H) surface. Atomic layer deposition (ALD) of a high-dielectric-constant oxide at a low temperature is conducted in the range of 25-200° C. to form an oxide layer. Annealing is conducted at an elevated temperature. A method for oxide deposition on a damage sensitive III_V semiconductor surface conducts in-situ cleaning of the surface with cyclic pulsing of hydrogen and TMA (trimethyl aluminum) at a low temperature in the range of 100-200° C. Atomic layer deposition (ALD) of a high-dielectric-constant oxide forms an oxide layer. Annealing is conducted at an elevated temperature. The annealing can create a silicon terminated interfaces.

Abstract translation: 在栅极氧化物沉积之前对SiGe或Ge表面的表面预处理清洁SiGe或Ge表面以提供氢封端表面或硫钝化（或S-H）表面。 在25-200℃的范围内进行低温下的高介电常数氧化物的原子层沉积（ALD），形成氧化物层。 退火在升高的温度下进行。 在损伤敏感的III_V半导体表面上的氧化物沉积的方法在100-200℃的低温下用氢和TMA（三甲基铝）的循环脉冲进行表面的原位清洗。原子层沉积（ALD ）的高介电常数氧化物形成氧化物层。 退火在升高的温度下进行。 退火可以产生硅封端的界面。