公开(公告)号：US20240215332A1

公开(公告)日：2024-06-27

申请号：US17908224

申请日：2021-11-04

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiayu HE ,  Ce NING ,  Zhengliang LI ,  Hehe HU ,  Fengjuan LIU ,  Wei LIU ,  Tianmin ZHOU ,  Kun ZHAO

IPC: H10K59/124 ,  H10K39/34 ,  H10K59/12

CPC classification number: H10K59/124 ,  H10K39/34 ,  H10K59/1201

Abstract: The present disclosure provides a display substrate and a preparation method thereof, and a display apparatus. The display substrate includes a circuit layer disposed on a base substrate, an emitting structure layer and a photoelectric structure layer disposed on a side of the circuit layer away from the base substrate, the circuit layer includes at least one impurity absorption layer and at least one transistor, the transistor includes an active layer, and at least one insulation layer is provided between the impurity absorption layer and the active layer; an atomic ratio of a silicon element to a nitrogen element in the impurity absorption layer is 1:5 to 1:35.

公开(公告)号：US20220223745A1

公开(公告)日：2022-07-14

申请号：US17761549

申请日：2021-05-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiayu HE ,  Ce NING ,  Zhengliang LI ,  Hehe HU ,  Jie HUANG ,  Nianqi YAO ,  Zhi WANG ,  Feng GUAN

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/06 ,  H01L29/66

Abstract: A thin film transistor, a manufacturing method thereof, a display substrate, and a display device are provided. The thin film transistor includes: a substrate, an active layer, a gate, a source and a drain. The active layer is arranged on the substrate and formed as a grid, including silicon nanowires extending along a first direction, the active layer includes source and drain regions oppositely arranged along the first direction, and a channel region located therebetween. The gate is arranged on the substrate, and an orthographic projection of the gate onto the substrate overlaps with orthographic projections for silicon nanowires in the channel region onto the substrate. The source and drain are arranged on the substrate, the source contacts silicon nanowires in the source region, and the drain contacts silicon nanowires in the drain region.

公开(公告)号：US20200286929A1

公开(公告)日：2020-09-10

申请号：US16318740

申请日：2018-04-02

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhengliang LI ,  Ce NING ,  Song LIU ,  Wenlin ZHANG ,  Xuefei SUN

IPC: H01L27/12

Abstract: The present disclosure provides a transistor, an array substrate and a method of manufacturing the array substrate, and a display device. The method of manufacturing the array substrate comprises: depositing a plurality of silicon oxide layers on an active layer of a transistor; and depositing a silicon oxynitride layer over the plurality of silicon oxide layers.

公开(公告)号：US20190094011A1

公开(公告)日：2019-03-28

申请号：US16041200

申请日：2018-07-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xuefei SUN ,  Chienhung LIU ,  Zhengliang LI ,  Bin ZHANG

IPC: G01B11/06

Abstract: The present disclosure provides a thickness measuring method and device. The thickness measuring method is used for measuring a thickness of a layer to be measured of a light-transmitting sample to be measured and comprising the steps of: placing the sample to be measured between an optical device and a metal layer, the optical device comprising a light incident surface and a light exit surface; adjusting incident light emitted to the light incident surface of the optical device so that an intensity of light exiting the light exit surface of the optical device is less than 10−12 W/m2, so as to obtain optical parameters of the incident light; and calculating a thickness of the layer to be measured according to the optical parameters of the incident light.

公开(公告)号：US20170294461A1

公开(公告)日：2017-10-12

申请号：US15325402

申请日：2016-03-09

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhanfeng CAO ,  Feng ZHANG ,  Bin ZHANG ,  Xiaolong HE ,  Zhengliang LI ,  Wei ZHANG ,  Feng GUAN ,  Jincheng GAO

IPC: H01L27/12

CPC classification number: H01L27/1262 ,  H01L21/77 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288

Abstract: A manufacturing method of an array substrate is provided. The method includes sequentially depositing a first electrode layer and a gate metal layer on a base substrate, the first electrode layer including at least two conductive layers, formation materials of the at least two conductive layers having different etching rates. The method also includes forming a photoresist layer on the gate metal layer, exposing and developing the photoresist layer using a halftone mask plate, performing a first etching process on the gate metal layer, etching the first electrode layer, and ashing the photoresist layer, performing a second etching process on the gate metal layer by using remaining photoresist layer as a mask, stripping the remaining photoresist layer, and sequentially forming a semiconductor layer, a source and drain electrode layer, a via-hole and a second electrode layer on the gate metal layer on which the second etching process has been performed.

公开(公告)号：US20170005110A1

公开(公告)日：2017-01-05

申请号：US15150549

申请日：2016-05-10

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhanfeng CAO ,  Feng ZHANG ,  Bin ZHANG ,  Xiaolong HE ,  Jincheng GAO ,  Qi YAO ,  Zhengliang LI ,  Xiangchun KONG

IPC: H01L27/12 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L27/124 ,  H01L29/41733 ,  H01L29/42384

Abstract: An array substrate and a display device are disclosed. The array substrate includes a peripheral area in which a plurality of gate electrode material lines, a plurality of source-drain electrode material lines and a plurality of first metal lines are disposed. Overlapping areas are provided between or among the gate electrode material lines, the source-drain material lines and the first metal lines; a number of the overlapping areas of the source-drain material lines and the first metal lines is less than a number of the overlapping areas of the source-drain material lines and the gate electrode material lines; the gate electrode material lines, the source-drain material lines and the first metal lines are configured as connecting lines of circuits in the peripheral area.

Abstract translation: 公开了阵列基板和显示装置。 阵列基板包括其中设置多个栅电极材料线，多个源极 - 漏极电极材料线和多个第一金属线的外围区域。 在栅电极材料线，源极 - 漏极材料线和第一金属线之间或之间提供重叠区域; 源极 - 漏极材料线和第一金属线的重叠区域的数量少于源极 - 漏极材料线和栅极材料线的重叠面积的数量; 栅电极材料线，源极 - 漏极材料线和第一金属线构成为周边区域中的电路的连接线。

公开(公告)号：US20160293658A1

公开(公告)日：2016-10-06

申请号：US14909712

申请日：2015-08-10

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Jincheng GAO ,  Zhanfeng CAO ,  Qi YAO ,  Zhengliang LI ,  Xiaolong HE ,  Bin ZHANG ,  Xiangchun KONG ,  Wei ZHANG

IPC: H01L27/146 ,  G01T1/24

CPC classification number: H01L27/14658 ,  G01T1/241 ,  G01T1/244 ,  H01L27/14612 ,  H01L27/14614 ,  H01L27/1462 ,  H01L27/14625 ,  H01L27/14636 ,  H01L27/14685 ,  H01L27/14689 ,  H01L27/14692

Abstract: The present disclosure discloses an X-ray flat-panel detector and a method for preparing the same, and a white insulating material. The X-ray flat-panel detector includes: a thin-film transistor substrate; an insulating reflection layer, which is provided on the thin-film transistor substrate and has a reflection function, wherein the insulating reflection layer is provided with a contact hole through which a source electrode of the thin-film transistor substrate is exposed; a pixel electrode, which is provided on the insulating reflection layer, wherein the pixel electrode is electrically connected to the source electrode of the thin-film transistor substrate via the contact hole; a photodiode, which covers the pixel electrode; an electrode, which is provided on the photodiode; and an X-ray conversion layer, which is provided on the electrode.

Abstract translation: 本公开公开了一种X射线平板检测器及其制备方法以及白色绝缘材料。 X射线平板检测器包括：薄膜晶体管基板; 绝缘反射层，其设置在所述薄膜晶体管基板上并具有反射功能，其中所述绝缘反射层设置有暴露所述薄膜晶体管基板的源电极的接触孔; 设置在所述绝缘反射层上的像素电极，所述像素电极经由所述接触孔与所述薄膜晶体管基板的源电极电连接; 覆盖像素电极的光电二极管; 设置在光电二极管上的电极; 以及设置在电极上的X射线转换层。

公开(公告)号：US20240379631A1

公开(公告)日：2024-11-14

申请号：US18691021

申请日：2021-10-22

Applicant: BOE Technology Group Co., Ltd.

Inventor： Nianqi YAO ,  Jin YANG ,  Ce NING ,  Jiayu HE ,  Jie HUANG ,  Hehe HU ,  Kun ZHAO ,  Feifei LI ,  Zhengliang LI ,  Guangcai YUAN

IPC: H01L27/12 ,  H01L25/16 ,  H01L33/62

Abstract: A light-emitting substrate and a display device are disclosed, the light-emitting substrate includes: a base substrate including a light-emitting region; a plurality of first pads on a side of the base substrate and in the light-emitting region, where a material of the first pads includes Cu; and an oxidation protection layer on a side of the first pads away from the base substrate, where the plurality of first pads is used for bonding connection with a plurality of light-emitting units through the oxidation protection layer, a material of the oxidation protection layer includes CuNiX, and X includes one or any combination of Al, Sn, Pb, Au, Ag, In, Zn, Bi, Mg, Ga, V, W, Y, Zr, Mo, Nb, Pt, Co or Sb.

公开(公告)号：US20240361628A1

公开(公告)日：2024-10-31

申请号：US18768052

申请日：2024-07-10

Applicant: BOE Technology Group Co., Ltd.

Inventor： Guangcai YUAN ,  Hehe HU ,  Changhan HSIEH ,  Shipei LI ,  Jiayu HE ,  Xin GU ,  Ce NING ,  Zhengliang LI

IPC: G02F1/133 ,  G02F1/1335 ,  G06F1/16 ,  H10K30/88

CPC classification number: G02F1/13318 ,  G02F1/133509 ,  G06F1/1652 ,  H10K30/88

Abstract: A photodetection backplane, a liquid crystal display panel and a liquid crystal display apparatus are provided. The photodetection backplane includes: a base substrate; a first organic switching unit arranged at a side of the base substrate; and an organic photodetector arranged at a same side of the base substrate as the first organic switching unit. The organic photodetector is electrically connected to the first organic switching unit, and at least one film layer of the organic photodetector and a film layer of the first organic switching unit are arranged in a same layer and made of a same material.
(FIG. 1)

公开(公告)号：US20240297243A1

公开(公告)日：2024-09-05

申请号：US18026833

申请日：2022-05-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiayu HE ,  Yan QU ,  Ce NING ,  Hehe HU ,  Zhengliang LI ,  Nianqi YAO ,  Jie HUANG ,  Kun ZHAO ,  Feifei LI ,  Liping LEI

IPC: H01L29/739 ,  H01L27/092 ,  H01L29/08 ,  H01L29/165 ,  H01L29/66 ,  H01L29/73

CPC classification number: H01L29/7391 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66356 ,  H01L29/7311

Abstract: A tunneling field effect transistor includes a gate electrode, a tunneling field active layer, a first electrode, and a second electrode disposed on a base substrate; the tunneling field active layer includes a first-type active layer and a second-type active layer that are stacked, wherein the first-type active layer includes a first-type channel region and a first source-drain region, the second-type active layer includes a second-type channel region and a second source-drain region, an orthographic projection of the first-type channel region on the base substrate is completely overlapped with an orthographic projection of the second-type channel region on the base substrate, the first source-drain region is located at a side of the tunneling field active layer and is connected with the first electrode.