公开(公告)号：US20220223745A1

公开(公告)日：2022-07-14

申请号：US17761549

申请日：2021-05-18

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jiayu HE ,  Ce NING ,  Zhengliang LI ,  Hehe HU ,  Jie HUANG ,  Nianqi YAO ,  Zhi WANG ,  Feng GUAN

IPC: H01L29/786 ,  H01L29/417 ,  H01L29/06 ,  H01L29/66

Abstract: A thin film transistor, a manufacturing method thereof, a display substrate, and a display device are provided. The thin film transistor includes: a substrate, an active layer, a gate, a source and a drain. The active layer is arranged on the substrate and formed as a grid, including silicon nanowires extending along a first direction, the active layer includes source and drain regions oppositely arranged along the first direction, and a channel region located therebetween. The gate is arranged on the substrate, and an orthographic projection of the gate onto the substrate overlaps with orthographic projections for silicon nanowires in the channel region onto the substrate. The source and drain are arranged on the substrate, the source contacts silicon nanowires in the source region, and the drain contacts silicon nanowires in the drain region.

公开(公告)号：US20210005769A1

公开(公告)日：2021-01-07

申请号：US16909526

申请日：2020-06-23

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chao LI ,  Jianhua DU ,  Feng GUAN ,  Yupeng GAO ,  Zhaohui QIANG ,  Zhi WANG ,  Yang LYU ,  Chao LUO

IPC: H01L31/105 ,  H01L27/12 ,  H01L31/12 ,  H01L31/18

Abstract: The present disclosure discloses a photoelectric detector, a preparation method thereof, a display panel and a display device. The photoelectric detector includes a base, and a thin film transistor (TFT) and a photosensitive PIN device on the base, wherein the PIN device includes an I-type region that does not overlap with an orthographic projection of the TFT on the base; a first etching barrier layer covering a top surface of the I-type region; a first heavily doped region in contact with a side surface on a side, proximate to the TFT, of the I-type region; and a second heavily doped region in contact with a side surface on a side, away from the TFT, of the I-type region, the doping types of the first heavily doped region and the second heavily doped region being different from each other.

公开(公告)号：US20180021987A1

公开(公告)日：2018-01-25

申请号：US15650016

申请日：2017-07-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Feng GUAN ,  Jikai YAO ,  Yingtao WANG ,  Xiaolong HE ,  Tingting ZHOU

IPC: B29C37/00 ,  B81C1/00 ,  B29C43/00 ,  G03F7/00

CPC classification number: B29C37/0053 ,  B29C43/003 ,  B81C1/0046 ,  G03B2217/242 ,  G03F7/0002

Abstract: The embodiments of the present disclosure provide an imprint template, a detection method and a detection device. The imprint template includes a first region and a second region located in the periphery of the first region. The first region is provided with a first imprint structure configured to imprint a first film layer pattern into a base material in a product region of a target substrate. The second region is provided with a second imprint structure configured to imprint a second film layer pattern into the base material in the periphery of the product region of the target substrate. And the second film layer pattern is used for assessing imprint quality of the first film layer pattern.

公开(公告)号：US20170294461A1

公开(公告)日：2017-10-12

申请号：US15325402

申请日：2016-03-09

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhanfeng CAO ,  Feng ZHANG ,  Bin ZHANG ,  Xiaolong HE ,  Zhengliang LI ,  Wei ZHANG ,  Feng GUAN ,  Jincheng GAO

IPC: H01L27/12

CPC classification number: H01L27/1262 ,  H01L21/77 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1288

Abstract: A manufacturing method of an array substrate is provided. The method includes sequentially depositing a first electrode layer and a gate metal layer on a base substrate, the first electrode layer including at least two conductive layers, formation materials of the at least two conductive layers having different etching rates. The method also includes forming a photoresist layer on the gate metal layer, exposing and developing the photoresist layer using a halftone mask plate, performing a first etching process on the gate metal layer, etching the first electrode layer, and ashing the photoresist layer, performing a second etching process on the gate metal layer by using remaining photoresist layer as a mask, stripping the remaining photoresist layer, and sequentially forming a semiconductor layer, a source and drain electrode layer, a via-hole and a second electrode layer on the gate metal layer on which the second etching process has been performed.

公开(公告)号：US20240251598A1

公开(公告)日：2024-07-25

申请号：US18017642

申请日：2022-01-28

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Feng GUAN

IPC: H10K59/121 ,  H10K59/12

CPC classification number: H10K59/1213 ,  H10K59/1201

Abstract: A display substrate is provided to include a base substrate and: a first transistor layer including a first active layer and a second transistor layer including a second active layer sequentially along a direction away from the base substrate; the first and second active layers are provided with at least one insulating layer therebetween, and are made of low-temperature polysilicon materials; the first active layer includes first channel region(s) and first source-drain doped region(s); the second active layer includes second channel region(s) and second source-drain doped region(s); orthographic projections of a second source-drain doped region and a first source-drain doped region on the base substrate overlap with each other; and a second source-drain doped region is connected to a first source-drain doped region through a connecting part filled in a corresponding first via in the insulating layer. A method for manufacturing a display substrate and a display apparatus are provided.

公开(公告)号：US20210335834A1

公开(公告)日：2021-10-28

申请号：US16607932

申请日：2019-04-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Feng GUAN

IPC: H01L27/12

Abstract: A display substrate, a display apparatus, and a manufacturing method of the display substrate are provided. The display substrate includes: a base substrate; and a crystallization induction layer and a polysilicon layer stacked on the base substrate. The crystallization induction layer includes induction layer patterns and intervals between the induction layer patterns. The polysilicon layer includes a portion overlapping the induction layer patterns and a portion overlapping the intervals, a crystallinity of the portion of the polysilicon layer overlapping the induction layer patterns is larger than a crystallinity of the portion of the polysilicon layer overlapping the intervals.

公开(公告)号：US20210151605A1

公开(公告)日：2021-05-20

申请号：US16642638

申请日：2019-03-04

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhi WANG ,  Guangcai YUAN ,  Feng GUAN ,  Chen XU ,  Xueyong WANG ,  Jianhua DU ,  Chao LI ,  Lei CHEN

IPC: H01L29/786 ,  H01L29/66

Abstract: The present disclosure relates to a thin film transistor and a manufacturing method thereof. The thin film transistor includes a substrate, a first semiconductor layer, a gate dielectric layer, and a gate electrode sequentially stacked on the substrate, the first semiconductor layer has a first portion located in a channel region of the thin film transistor and a second portion in source/drain regions of the thin film transistor and located on both sides of the first portion, the second portion and first sub-portions of the first portion adjacent to the second portion include an amorphous semiconductor material, a second sub-portion of the first portion between the first sub-portions includes a polycrystalline semiconductor material, and a second semiconductor layer located in the source/drain regions and in contact with the second portion, wherein a conductivity of the second semiconductor layer is higher than a conductivity of the amorphous semiconductor material.

公开(公告)号：US20210111200A1

公开(公告)日：2021-04-15

申请号：US16846888

申请日：2020-04-13

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yupeng GAO ,  Guangcai YUAN ,  Feng GUAN ,  Zhi WANG ,  Jianhua DU ,  Zhaohui QIANG ,  Chao LI

IPC: H01L27/12 ,  H01L29/24 ,  H01L29/786 ,  H01L29/66

Abstract: The present disclosure discloses a method for preparing an array substrate, an array substrate and a display panel, wherein the method comprises: forming a buffer layer on a substrate in a first region and a second region, wherein the buffer layer has a groove located in the second region; forming a first indium oxide thin film on the buffer layer in the first region; forming a second indium oxide thin film in the groove; performing a reduction process on the second indium oxide thin film to obtain indium particles; forming an amorphous silicon thin film in the groove, and inducing the amorphous silicon of the amorphous silicon thin film to form microcrystalline silicon at a preset temperature by using the indium particles; and removing the indium particles in the microcrystalline silicon to form a microcrystalline silicon semiconductor layer of the microcrystalline silicon thin film transistor.

公开(公告)号：US20190019968A1

公开(公告)日：2019-01-17

申请号：US15749761

申请日：2017-06-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiaolong HE ,  Yingtao WANG ,  Feng GUAN ,  Jikai YAO

IPC: H01L51/50 ,  H01L51/52 ,  H01L51/56 ,  G02F1/1335 ,  G02B27/30

Abstract: The embodiments of the present disclosure disclose a collimated light source, a manufacturing method thereof and a display device. The collimated light source includes a substrate, a film layer with a plurality of concave microstructures on the substrate, a reflective layer on the film layer, and a plurality of light-emitting parts corresponding to the concave microstructures one-to-one. Each of the light-emitting parts is located at a focal point of a corresponding concave microstructure. According to the embodiments of the present disclosure, the light emitted from each light-emitting part is reflected by the reflective layer on the corresponding concave microstructure and then exits in parallel light from a side of the reflective layer facing away from the substrate.

公开(公告)号：US20180050483A1

公开(公告)日：2018-02-22

申请号：US15680614

申请日：2017-08-18

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Feng GUAN ,  Jikai YAO ,  Xiaolong HE ,  Hua HUANG

IPC: B29C59/02 ,  G03F7/00

CPC classification number: B29C59/02 ,  B29C59/022 ,  B29C59/026 ,  B29C2035/0827 ,  B29C2059/023 ,  B29C2791/006 ,  B29C2791/007 ,  G03F7/0002

Abstract: An imprinting device and an imprinting method using the same are disclosed. The imprinting device includes: a chamber body and a base, which are able to combine with each other to form an imprinting chamber, the imprinting chamber being divided into a first chamber and a second chamber by a dividing film; and a movable supporting member, configured to support an imprinting stencil inside the second chamber, and to allow the imprinting stencil to: under the drive of gas pressure within the imprinting chamber, contact a substrate to be imprinted and apply a pressure to the substrate. The imprinting technical provided by the present disclosure decreases bubble defect rate, improves uniformity of large area imprinting, and makes possible large area nano-imprinting technology.