公开(公告)号：US10049762B2

公开(公告)日：2018-08-14

申请号：US15532343

申请日：2016-09-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang

IPC: G11C19/18 ,  G11C19/28 ,  G09G3/20

Abstract: Disclosed are a shift register unit, an operation method therefor and a shift register including the shift register unit. The shift register unit includes: an input module configured to transmit a received input signal to a pull-up node; an output module configured to output a first control signal of a first control signal end to an output end when a pull-up signal at the pull-up node is at an effective pull-up level; and a coupling module having a first end connected to a second control signal end and a second end connected to the pull-up node, and being configured to control the pull-up signal at the pull-up node in a voltage coupling manner according to a second control signal of the second control signal end. By further pulling up the voltage at the pull-up node when output end is reset, the speed of resetting the output end can be increased.

公开(公告)号：US10006957B2

公开(公告)日：2018-06-26

申请号：US14573100

申请日：2014-12-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Yun Sik Im ,  Seung Woo Han

IPC: G01R31/26 ,  H01L21/66

CPC classification number: G01R31/2621 ,  G01R31/2608 ,  H01L22/34

Abstract: A circuit and method for testing transistor(s) are provided. The circuit is used for testing a set of transistors including at least two transistors, and the circuit includes: a first power supply voltage terminal connected to first electrodes of the respective transistors; a first control signal terminal connected to control electrodes of the respective transistors; and a set of test terminals including at least two test terminals; the test terminals are connected to second electrodes of the corresponding transistors, respectively.

公开(公告)号：US20180108426A1

公开(公告)日：2018-04-19

申请号：US15504119

申请日：2016-08-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Haoliang Zheng ,  Seungwoo Han ,  Xing Yao ,  Hyunsic Choi ,  Guangliang Shang ,  Mingfu Han ,  Yunsik Im ,  Jungmok JUN ,  Xue Dong

IPC: G11C19/28 ,  G09G3/36 ,  H01L27/12 ,  G11C19/18

CPC classification number: G11C19/28 ,  G09G3/20 ,  G09G3/3677 ,  G09G3/3688 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/184 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1251

Abstract: The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK1/CLK2, a second bias-control terminal to receive a second/first bias signal CLK2/CLK1, and a first control level terminal provided with a first control voltage VC1, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK3/CLK4, a fourth bias-control terminal to receive a fourth/third bias signal CLK4/CLK3, and a second control level terminal provided with a second control voltage VC2; configuring the first bias signal CLK1 and the second bias signal CLK2 as first pair of clock signals at respective turn-on level and turn-off level with inverted phase in the first sub-cycle; setting the first control voltage VC1 to a turn-off level so that the first plurality of shift register units is controlled along with the first pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the first sub-cycle; setting both the third bias signal CLK3 and the fourth bias signal CLK4 to a turn-off level and the second control voltage VC2 to turn-on level during the first sub-cycle; configuring the third bias signal CLK3 and the fourth bias signal CLK4 as second pair of clock signals at respective turn-on level and turn-off level with inverted phase in the second sub-cycle; setting the second control voltage VC2 to a turn-off level so that the second plurality of shift register units are controlled along with the second pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the second sub-cycle; and setting the first bias signal CLK1 and the second bias signal CLK2 to a turn-off level and the second control voltage VC1 to a turn-on level during the second sub-cycle.

公开(公告)号：US20170270851A1

公开(公告)日：2017-09-21

申请号：US15503051

申请日：2016-08-04

Applicant: Boe Technology Group Co., Ltd.

Inventor： Guangliang Shang ,  Seungwoo Han ,  Zhihe Jin ,  Mingfu Han ,  Xing Yao ,  Haoling Zheng ,  Yunsil IM ,  Seungmin Lee ,  Haijun Qiu ,  Jungmok Jun ,  Xue Dong

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/08 ,  G11C19/28

Abstract: A shift register is disclosed including an input module, an output module, a first reset module, a first pull-down module and a second pull-down module. The first pull-down module is configured to supply a reference signal to a first node and an output terminal in response to an active level of a first control signal. The second pull-down module is configured to supply the reference signal to the first node and the output terminal in response to an active level of a second control signal. The active levels of the first control signal and the second control signal occur alternately. Also disclosed are a gate driver circuit and a display apparatus.

公开(公告)号：US09443458B2

公开(公告)日：2016-09-13

申请号：US14340193

申请日：2014-07-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang

IPC: G09G3/20 ,  G11C19/28

CPC classification number: G09G3/20 ,  G09G2310/0267 ,  G11C19/28

Abstract: The embodiments of the present invention provide a driving circuit and a driving method, a GOA unit, a GOA circuit and a display device, to improve the response speed of the circuit and reduce the leakage current. This driving circuit comprises: at least one pull-up/pull-down unit each configured to pull up or pull down a voltage of a controlled node; each pull-up/pull-down unit comprises at least one double-gate transistor, the double-gate transistor is used to accelerate the charge or discharge of the node when being turned on, or is used to reduce the leakage current passing the node when being turned off. The embodiments of the present invention are suitable to be applied to the display production.

Abstract translation: 本发明的实施例提供驱动电路和驱动方法，GOA单元，GOA电路和显示装置，以提高电路的响应速度并减少漏电流。 该驱动电路包括：至少一个上拉/下拉单元，每个上拉/下拉单元被配置为上拉或下拉受控节点的电压; 每个上拉/下拉单元包括至少一个双栅极晶体管，双栅极晶体管用于在导通时加速节点的充电或放电，或者用于减少通过节点的漏电流 当被关闭。 本发明的实施例适用于显示器生产。

公开(公告)号：US09437145B2

公开(公告)日：2016-09-06

申请号：US14497385

申请日：2014-09-26

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Seungwoo Han ,  Yuanbo Zhang ,  Guangliang Shang

IPC: G09G3/36

CPC classification number: G09G3/3607 ,  G09G3/3696 ,  G09G2300/0408 ,  G09G2310/027 ,  G09G2320/0233 ,  G09G2320/0276 ,  G09G2320/0673 ,  G09G2330/06

Abstract: The present disclosure provides a gamma reference voltage generating circuit including a center voltage generation unit, a gamma reference voltage generation unit configured to generate positive and negative gamma reference voltages and control the positive gamma reference voltage and the negative gamma reference voltage to be symmetrical with respect to the center voltage; a first voltage divider unit including a first terminal for receiving the positive gamma reference voltage and a second terminal for receiving the center voltage; and a second voltage divider unit including a first terminal coupled with the second terminal of the first voltage divider unit and a second terminal for receiving the negative gamma reference voltage.

Abstract translation: 本公开提供了一种伽马参考电压产生电路，其包括中心电压产生单元，伽马参考电压产生单元，被配置为产生正和负伽马参考电压，并且控制正伽马参考电压和负伽马参考电压相对于对称 到中心电压; 第一分压器单元，包括用于接收正伽马参考电压的第一端子和用于接收中心电压的第二端子; 以及第二分压器单元，包括与第一分压器单元的第二端子耦合的第一端子和用于接收负的伽马参考电压的第二端子。

公开(公告)号：US08976922B2

公开(公告)日：2015-03-10

申请号：US13704141

申请日：2012-10-29

Applicant: Boe Technology Group Co., Ltd.

Inventor： Guangliang Shang

IPC: G11C19/00 ,  G11C19/28 ,  G09G3/36

CPC classification number: G11C19/28 ,  G09G3/3611 ,  G09G2310/0286

Abstract: The present invention provides a shift register unit, a shift register circuit, an array substrate and a display device, and relates to the area of display manufacturing. The time of the bias working on the de-noising transistor can be reduced without affecting the circuit stability, so that the operational lifespan of the device can be extended. A shift register comprises: a capacitor, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a de-noising control model. The present invention is used for manufacturing displays.

Abstract translation: 本发明提供一种移位寄存器单元，移位寄存器电路，阵列基板和显示器件，涉及显示器制造领域。 可以减少在去噪晶体管上工作的偏置的时间，而不会影响电路的稳定性，从而可以延长器件的工作寿命。 移位寄存器包括：电容器，第一晶体管，第二晶体管，第三晶体管，第四晶体管，第五晶体管，第六晶体管，去噪控制模型。 本发明用于制造显示器。

公开(公告)号：US20140118422A1

公开(公告)日：2014-05-01

申请号：US14127108

申请日：2012-11-30

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Guangliang Shang ,  Jing Lv

IPC: G09G3/36 ,  G09G5/10

CPC classification number: G09G3/3611 ,  G09G5/10 ,  G09G2310/0243 ,  G09G2340/0435 ,  H04N13/359 ,  H04N13/398

Abstract: Provided are an image display device and an image display method, which is capable of increasing charging period and reducing switching frequency of driving data while performing display device driving. The image display device comprises combined pixels of m columns and n rows, wherein each of the combined pixels comprises a first row of sub-pixels and a second row of sub-pixels beneath the first row of sub-pixels, wherein in a 2D image display mode, both the first rows of sub-pixels and the second rows of sub-pixels in the respective rows of combined pixels are driven and receive 2D display data; and in a 3D image display mode, one row of sub-pixels in the respective rows of combined pixels receives data and the other row of sub-pixels in the respective rows of combined pixels do not receive data.

Abstract translation: 提供一种图像显示装置和图像显示方法，其能够在执行显示装置驱动的同时增加充电周期并降低驱动数据的开关频率。 图像显示装置包括m列和n行的组合像素，其中每个组合像素包括第一行子像素行和第一排子像素下方的第二排子像素，其中在2D图像中 显示模式，驱动组合像素的各行中的第一行子像素和第二行子像素，并接收2D显示数据; 并且在3D图像显示模式中，组合像素的各行中的一行子像素接收数据，并且组合像素的各行中的另一排子像素不接收数据。

公开(公告)号：US20140072093A1

公开(公告)日：2014-03-13

申请号：US13995672

申请日：2012-12-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD

Inventor： Guangliang Shang ,  Seung Woo Han ,  Jiayang Zhao

IPC: G11C19/18

CPC classification number: G11C19/184 ,  G09G3/20 ,  G09G3/3266 ,  G09G3/3688 ,  G09G2310/0283 ,  G09G2310/0286 ,  G09G2310/061 ,  G09G2320/0223 ,  G11C19/28

Abstract: A shift register is used for solving the problem that the shift register in the prior art can only perform a forward scanning driving but can not perform a bi-directional scanning driving. The shift register includes: a first TFT(T1), a second TFT(T2), a reset unit and a pulling-up unit. The present disclosure further provides a display including the shift register. The shift register and the display can achieve a bi-directional scanning driving.

Abstract translation: 移位寄存器用于解决现有技术中的移位寄存器只能执行正向扫描驱动但不能执行双向扫描驱动的问题。 移位寄存器包括：第一TFT（T1），第二TFT（T2），复位单元和上拉单元。 本公开还提供了包括移位寄存器的显示器。 移位寄存器和显示器可以实现双向扫描驱动。

公开(公告)号：US12293049B2

公开(公告)日：2025-05-06

申请号：US18031282

申请日：2022-05-31

Applicant: BOE Technology Group Co., Ltd.

Inventor： Hao Liu ,  Jianchao Zhu ,  Mengyang Wen ,  Zibo Ni ,  Guangliang Shang ,  Libin Liu

IPC: G06F3/044 ,  G06F3/041 ,  G06F3/045

Abstract: The present disclosure provides a touch display panel. The touch display panel includes a display substrate and a touch layer, wherein the touch layer includes a plurality of touch units and a plurality of touch lines which are disposed on the display substrate; wherein the touch lines are connected to at least one touch unit and are configured to electrically connect the touch unit connected thereto to a touch integrated circuit; the plurality of touch lines at least include a first trace and a second trace which are disposed in a non-display region, a length of the first trace being greater than a length of the second trace, and a cross-sectional area of the first trace being larger than a cross-sectional area of the second trace.