公开(公告)号：US20080159382A1

公开(公告)日：2008-07-03

申请号：US12049433

申请日：2008-03-17

Applicant: Bryan Kris

Inventor： Bryan Kris

IPC: H03K7/08

CPC classification number: H03K7/08

Abstract: A pulse width modulation (PWM) generator featuring very high speed and high resolution capability and the ability to generate standard complementary PWM, push-pull PWM, variable offset PWM, multiphase PWM, current limit PWM, current reset PWM, and independent time base PWM while further providing automatic triggering for an analog-to-digital conversion (ADC) module that is precisely timed relative to the PWM signals. Applications include control of a switching power supply that requires very high speed operation to obtain high resolution at high switching frequencies, and the ability to vary the phase relationships among the PWM output signals driving the power supply power components. A single PWM duty cycle register may be used for updating any and/or all PWM generators at once to reduce the workload of a digital processor as compared to updating multiple duty cycle registers.

Abstract translation: 脉宽调制（PWM）发生器具有非常高的速度和高分辨率能力，能够产生标准互补PWM，推挽PWM，可变偏移PWM，多相PWM，限流PWM，电流复位PWM和独立时基PWM 同时进一步提供相对于PWM信号精确定时的模数转换（ADC）模块的自动触发。 应用包括控制开关电源，其需要非常高的速度操作以在高开关频率下获得高分辨率，以及改变驱动电源功率部件的PWM输出信号之间的相位关系的能力。 与更新多个占空比寄存器相比，可以使用单个PWM占空比寄存器来一次更新任何和/或所有PWM发生器，以减少数字处理器的工作负载。

公开(公告)号：US20070230559A1

公开(公告)日：2007-10-04

申请号：US11620499

申请日：2007-01-05

Applicant: Bryan Kris ,  Steve Bradley

Inventor： Bryan Kris ,  Steve Bradley

IPC: H03K7/08

CPC classification number: H03K7/08

Abstract: A pulse width modulation (PWM) generator having asynchronous updating of its PWM duty cycle and/or period values allows immediate correction for the new PWM duty cycle and/or period values instead of waiting until the end of a PWM period to accept the new duty cycle and/or period values. This reduces the latency in a control loop when responding to changing system status, e.g., changes in PWM duty cycle. Also the PWM duty cycle is prevented from “running away” (e.g., missing a PWM cycle) if the PWM duty cycle timer/counter has advanced beyond an updated duty-cycle maximum value.

Abstract translation: 具有异步更新其PWM占空比和/或周期值的脉冲宽度调制（PWM）发生器允许立即校正新的PWM占空比和/或周期值，而不是等待直到PWM周期结束以接受新的占空比 周期和/或周期值。 这减少了响应于改变的系统状态（例如，PWM占空比的变化）时控制回路中的等待时间。 此外，如果PWM占空比定时器/计数器已超出更新的占空比最大值，则PWM占空比也不会“运行”（例如，缺少PWM周期）。

公开(公告)号：US07177166B1

公开(公告)日：2007-02-13

申请号：US11215622

申请日：2005-08-30

Applicant: Bryan Kris

Inventor： Bryan Kris

IPC: H02M1/12 ,  H02M1/14

CPC classification number: H02M1/12 ,  H02M1/44

Abstract: A switch mode power supply has pulse width modulation (PWM) frequency dithering of a PWM clock frequency. The PWM frequency dithering circuit may change the frequency of the PWM clock based upon each of a plurality of frequencies. A PWM time base circuit may comprise a period register containing a PWM period value, a comparator, and a PWM counter, wherein a PWM count value may be incremented in the PWM counter by the variable frequency PWM clock, the comparator may compare the PWM period value with the PWM count value and when the PWM period value and the PWM count value are substantially equal the PWM count value may be reset. The PWM frequency dithering circuit may comprise a roll counter, wherein the roll counter changes a roll count value each time the comparator resets the PWM count value in the PWM counter; a multiplexer having a plurality of inputs and an output, wherein the output is coupled to each one of the plurality of inputs of the multiplexer based upon the roll counter count value; and a plurality of frequency registers, each one of the plurality of frequency registers may be coupled to a respective one of the plurality of inputs of the multiplexer; wherein the output of the multiplexer may be coupled to a frequency control input of the variable frequency PWM clock such that frequency values stored in the plurality of frequency registers may be used in determining the variable frequency PWM clock frequency.

Abstract translation: 开关模式电源具有PWM时钟频率的脉宽调制（PWM）频率抖动。 PWM频率抖动电路可以基于多个频率中的每一个来改变PWM时钟的频率。 PWM时基电路可以包括包含PWM周期值的周期寄存器，比较器和PWM计数器，其中PWM计数值可以在PWM计数器中通过可变频率PWM时钟递增，比较器可以比较PWM周期 具有PWM计数值的值，并且当PWM周期值和PWM计数值基本相等时，可以复位PWM计数值。 PWM频率抖动电路可以包括滚动计数器，其中每当比较器复位PWM计数器中的PWM计数值时，滚转计数器改变滚动计数值; 多路复用器，具有多个输入和输出，其中所述输出基于所述滚转计数器计数值耦合到所述多路复用器的多个输入中的每一个; 和多个频率寄存器，多个频率寄存器中的每一个可以耦合到多路复用器的多个输入中的相应一个; 其中多路复用器的输出可以耦合到可变频率PWM时钟的频率控制输入，使得存储在多个频率寄存器中的频率值可以用于确定可变频率PWM时钟频率。

公开(公告)号：US20130147446A1

公开(公告)日：2013-06-13

申请号：US13313296

申请日：2011-12-07

Applicant: Bryan Kris ,  Joseph W. Triece ,  J. Clark Rogers ,  Pieter Schieke

Inventor： Bryan Kris ,  Joseph W. Triece ,  J. Clark Rogers ,  Pieter Schieke

IPC: G05F1/10

CPC classification number: G06F1/26 ,  G06F1/3203 ,  H02M2001/0045

Abstract: An integrated circuit device has a digital device operating at an internal core voltage; a linear voltage regulator; and an internal switched mode voltage regulator controlled by the digital device and receiving an external supply voltage being higher than the internal core voltage through at least first and second external pins and generating the internal core voltage, wherein the internal switched mode voltage regulator is coupled with at least one external component through at least one further external pin of the plurality of external pins.

Abstract translation: 集成电路器件具有以内部核心电压工作的数字器件; 线性稳压器; 以及由数字设备控制的内部开关模式电压调节器，并且通过至少第一和第二外部引脚接收高于内部电压的外部电源电压并产生内部电源电压，其中内部开关模式电压调节器与 通过所述多个外部引脚中的至少一个另外的外部引脚的至少一个外部部件。

公开(公告)号：US08432208B2

公开(公告)日：2013-04-30

申请号：US13247636

申请日：2011-09-28

Applicant: Bryan Kris

Inventor： Bryan Kris

IPC: H03K3/017 ,  H03K9/08 ,  H03K7/08

CPC classification number: H03K7/08 ,  H02M3/1584 ,  H03K19/00315 ,  H04L25/4902

Abstract: Multi-phase, frequency coherent pulse width modulation (PWM) signals are generated that maintain PWM data-set coherency regardless of user or system events. PWM data-set coherency is accomplished by adding data buffers to hold and transfer new PWM data during a data-set update from a processor. After the data-set transfer to the data buffers is complete and when the next PWM cycle is about to start, the data-set stored in the data buffers is transferred to the active PWM registers in time for the start of the next PWM cycle.

Abstract translation: 生成多相，频率相干脉宽调制（PWM）信号，无论用户或系统事件如何，均可维持PWM数据集的一致性。 PWM数据集的一致性是通过在处理器的数据集更新期间添加数据缓冲器来保存和传输新的PWM数据来实现的。 在数据传输到数据缓冲区完成之后，当下一个PWM周期即将开始时，数据缓冲器中存储的数据组将及时传送到有源PWM寄存器，以便下一个PWM周期的开始。

公开(公告)号：US07714626B2

公开(公告)日：2010-05-11

申请号：US12045759

申请日：2008-03-11

Applicant: Bryan Kris

Inventor： Bryan Kris

IPC: H03K3/017

CPC classification number: H03K7/08 ,  H03K3/017 ,  H03M1/68 ,  H03M1/822

Abstract: Using a combination of frequency dithering of a PWM counter and a variable time delay circuit yields improved PWM frequency resolution with realizable circuit components and clock operating frequencies. A controllable time delay circuit lengthens a PWM signal during the first PWM cycle. During the second PWM cycle, the PWM period is increased beyond the desired amount, but the delay is reduced during this second PWM cycle to achieve the correct (desired) PWM signal period. The dithering of the PWM signal period enables the time delay circuit to be “reset” so that an infinite delay circuit is not required. The time delay circuit provides short term (one cycle) frequency adjustment so that the resulting PWM cycle is not dithered and has a period at the desired frequency resolution.

Abstract translation: 使用PWM计数器的频率抖动和可变时间延迟电路的组合可以实现可实现的电路组件和时钟工作频率的改进的PWM频率分辨率。 可控延时电路在第一个PWM周期期间延长PWM信号。 在第二个PWM周期期间，PWM周期增加超过所需的量，但是在该第二个PWM周期期间延迟减小以实现正确的（期望的）PWM信号周期。 PWM信号周期的抖动使得时间延迟电路“复位”，从而不需要无限延迟电路。 时间延迟电路提供短期（一个周期）频率调整，使得所得到的PWM周期不抖动，并具有期望频率分辨率的周期。

公开(公告)号：US20090184742A1

公开(公告)日：2009-07-23

申请号：US12351371

申请日：2009-01-09

Applicant: Bryan Kris

Inventor： Bryan Kris

IPC: H03L7/00

CPC classification number: H03K7/08

Abstract: Waveform errors between multiphase PWM signals caused by external synchronization signals is solved by providing a capture register in a master time base circuit. The capture register is triggered by the external sync signal so as to “capture” the value of the master time base counter at the occurrence of the rising edge of the external sync signal. This captured counter value is then provided to the local time bases of each of the phase PMW signal generators as the effective PWM period instead of locally stored PWM period values of each PWM signal generator. The captured time base value provided to the individual PWM generator time bases insures that the individual PWM generators remain properly synchronized to the master time base throughout the PWM cycles of all of the phases.

Abstract translation: 通过在主时基电路中提供捕获寄存器来解决由外部同步信号引起的多相PWM信号之间的波形误差。 捕获寄存器由外部同步信号触发，以便在外部同步信号的上升沿出现时捕获主时基计数器的值。 然后将该捕获的计数器值提供给每个相位PMW信号发生器的本地时基作为有效PWM周期，而不是每个PWM信号发生器的本地存储的PWM周期值。 提供给各个PWM发生器时基的捕获的时基值确保各个PWM发生器在所有相的整个PWM周期内保持与主时基的正确同步。

公开(公告)号：US20070094524A1

公开(公告)日：2007-04-26

申请号：US11385377

申请日：2006-03-21

Applicant: Bryan Kris

Inventor： Bryan Kris

IPC: G06F1/00

CPC classification number: H02J1/102

Abstract: A plurality of power supply modules having their outputs coupled in parallel are controlled for load balancing purposes through a digital communications channel. The digital communications channel may be a wired digital serial or parallel bus, and/or a wireless digital communications channel such as Bluetooth, infrared, etc. Each of the plurality of power supply modules may broadcast their respective output currents and all of the plurality of power supply modules may determine a total current supplied to a load and thereby determine an appropriate output voltage for proportionally contributing to the total current.

Abstract translation: 通过数字通信信道来控制具有并联耦合的多个电源模块用于负载平衡目的。 数字通信信道可以是有线数字串行或并行总线，和/或诸如蓝牙，红外等的无线数字通信信道。多个电源模块中的每一个可以广播它们各自的输出电流，并且所有多个 电源模块可以确定提供给负载的总电流，从而确定适当的输出电压以对总电流进行比例的贡献。

公开(公告)号：US07157890B1

公开(公告)日：2007-01-02

申请号：US11385374

申请日：2006-03-21

Applicant: Bryan Kris

Inventor： Bryan Kris

IPC: G05F1/595

CPC classification number: H02J1/102

Abstract: A plurality of power supply modules having their outputs coupled in parallel are controlled for load balancing purposes through a direct current bus having filtered pulse width modulation (PWM) signals representative of the power outputs of each of the plurality of power supply modules. A local PWM signal for each of the plurality of power supply modules is filtered to a DC voltage and used to compare with an average power required from each of the plurality of power supply modules.

Abstract translation: 通过具有代表多个电源模块中每个电源模块的功率输出的已滤波的脉冲宽度调制（PWM）信号的直流总线，控制具有并联耦合的多个电源模块用于负载平衡目的。 用于多个电源模块中的每一个的本地PWM信号被滤波成DC电压并用于与多个电源模块中的每一个所需的平均功率进行比较。

公开(公告)号：US06552567B1

公开(公告)日：2003-04-22

申请号：US09964664

申请日：2001-09-28

Applicant: Brian Boles ,  Richard Fischer ,  Sumit Mitra ,  Rodney Drake ,  Stephen A. Bowling ,  Bryan Kris ,  Steven Marsh ,  Hassan Harb

Inventor： Brian Boles ,  Richard Fischer ,  Sumit Mitra ,  Rodney Drake ,  Stephen A. Bowling ,  Bryan Kris ,  Steven Marsh ,  Hassan Harb

IPC: H03K190175

CPC classification number: G06F15/76

Abstract: The present invention relates generally to functional pathway configurations at the interfaces between integrated circuits (ICs) and the circuit assemblies with which the ICs communicate. More particularly, the present invention relates generally to the functional pathway configuration at the interface between one or more semiconductor integrated circuit dice, including an IC package and the circuitry of a system wherein the integrated circuit dice is a digital signal controller. Even more particularly, the present invention relates to a 18, 28, 40, 44, 64 or 80 pin functional pathway configuration for the interface between the digital signal controller and the system in which it is embedded.

Abstract translation: 本发明一般涉及集成电路（IC）与IC连接的电路组件之间的接口上的功能通路配置。 更具体地说，本发明一般涉及包括IC封装的一个或多个半导体集成电路管芯与系统的电路之间的界面处的功能通路配置，其中集成电路管芯是数字信号控制器。 更具体地，本发明涉及用于数字信号控制器和嵌入其中的系统之间的接口的18,28,40,44,64或80引脚功能通路配置。