公开(公告)号：US20130147446A1

公开(公告)日：2013-06-13

申请号：US13313296

申请日：2011-12-07

申请人： Bryan Kris ,  Joseph W. Triece ,  J. Clark Rogers ,  Pieter Schieke

发明人： Bryan Kris ,  Joseph W. Triece ,  J. Clark Rogers ,  Pieter Schieke

IPC分类号： G05F1/10

CPC分类号： G06F1/26 ,  G06F1/3203 ,  H02M2001/0045

摘要： An integrated circuit device has a digital device operating at an internal core voltage; a linear voltage regulator; and an internal switched mode voltage regulator controlled by the digital device and receiving an external supply voltage being higher than the internal core voltage through at least first and second external pins and generating the internal core voltage, wherein the internal switched mode voltage regulator is coupled with at least one external component through at least one further external pin of the plurality of external pins.

摘要翻译： 集成电路器件具有以内部核心电压工作的数字器件; 线性稳压器; 以及由数字设备控制的内部开关模式电压调节器，并且通过至少第一和第二外部引脚接收高于内部电压的外部电源电压并产生内部电源电压，其中内部开关模式电压调节器与 通过所述多个外部引脚中的至少一个另外的外部引脚的至少一个外部部件。

公开(公告)号：US08779734B2

公开(公告)日：2014-07-15

申请号：US13313296

申请日：2011-12-07

申请人： Bryan Kris ,  Joseph W. Triece ,  J. Clark Rogers ,  Pieter Schieke

发明人： Bryan Kris ,  Joseph W. Triece ,  J. Clark Rogers ,  Pieter Schieke

IPC分类号： H02M3/158 ,  G05F1/59

CPC分类号： G06F1/26 ,  G06F1/3203 ,  H02M2001/0045

摘要： An integrated circuit device has a digital device operating at an internal core voltage; a linear voltage regulator; and an internal switched mode voltage regulator controlled by the digital device and receiving an external supply voltage being higher than the internal core voltage through at least first and second external pins and generating the internal core voltage, wherein the internal switched mode voltage regulator is coupled with at least one external component through at least one further external pin of the plurality of external pins.

摘要翻译： 集成电路器件具有以内部核心电压工作的数字器件; 线性稳压器; 以及由数字设备控制的内部开关模式电压调节器，并且通过至少第一和第二外部引脚接收高于内部电压的外部电源电压并产生内部电源电压，其中内部开关模式电压调节器与 通过所述多个外部引脚中的至少一个另外的外部引脚的至少一个外部部件。

公开(公告)号：US09208095B2

公开(公告)日：2015-12-08

申请号：US11928242

申请日：2007-10-30

申请人： Rodney J. Pesavento ,  Gregg D. Lahti ,  Joseph W. Triece

发明人： Rodney J. Pesavento ,  Gregg D. Lahti ,  Joseph W. Triece

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A cache module for a central processing unit has a cache control unit with an interface for a memory, a cache memory coupled with the control unit, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions or data, wherein the address tag bit field is readable and writeable and wherein the cache control unit is operable upon detecting that an address has been written to the address tag bit field to initiate a preload function in which instructions or data from the memory are loaded from the address into the at least one cache line.

摘要翻译： 一种用于中央处理单元的缓存模块具有一个具有用于存储器的接口的高速缓存控制单元，与控制单元耦合的高速缓冲存储器，其中高速缓冲存储器具有多条高速缓存行，多条高速缓存行中的至少一条高速缓存行 线路具有用于存储指令或数据的地址标签位字段和相关联的存储区域，其中地址标签位字段是可读写的，并且其中高速缓存控制单元在检测到地址已被写入地址标签位字段 以启动预载功能，其中来自存储器的指令或数据从地址加载到至少一个高速缓存行中。

公开(公告)号：US20100306457A1

公开(公告)日：2010-12-02

申请号：US12776046

申请日：2010-05-07

申请人： Tim L. Wilson ,  Joseph W. Triece ,  Steven G. Dawson

发明人： Tim L. Wilson ,  Joseph W. Triece ,  Steven G. Dawson

IPC分类号： G06F15/16 ,  G06F12/02

CPC分类号： H04L12/40013 ,  H04L12/4135 ,  H04L49/90 ,  H04L49/901 ,  H04L2012/40215

摘要： A microcontroller has a random access memory, and a Controller Area Network (CAN) controller with a control unit receiving an assembled CAN message. The control unit generates a buffer descriptor table entry using the assembled CAN message and stores the buffer descriptor table entry in the random access memory, and the buffer descriptor table entry has at least a message identifier and load data from the CAN message and information of a following buffer descriptor table entry.

摘要翻译： 微控制器具有随机存取存储器和控制器区域网络（CAN）控制器，控制单元接收组合的CAN消息。 控制单元使用组合的CAN消息生成缓冲器描述符表条目，并将缓冲器描述符表条目存储在随机存取存储器中，并且缓冲器描述符表条目至少具有来自CAN消息的消息标识符和加载数据，以及 跟随缓冲区描述符表项。

公开(公告)号：US07603601B2

公开(公告)日：2009-10-13

申请号：US11355619

申请日：2006-02-16

申请人： Cristian P. Masgras ,  Michael Pyska ,  Edward Brian Boles ,  Joseph W. Triece ,  Igor Wojewoda ,  Mei-Ling Chen

发明人： Cristian P. Masgras ,  Michael Pyska ,  Edward Brian Boles ,  Joseph W. Triece ,  Igor Wojewoda ,  Mei-Ling Chen

IPC分类号： G01R31/3185

CPC分类号： G01R31/31701 ,  G06F11/273 ,  G11C29/003 ,  G11C29/46

摘要： A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.

摘要翻译： 特殊模式键匹配比较模块具有N存储元件和特殊模式键匹配比较器。 N存储元件累积串行数据流，然后确定数字设备是否应该以普通用户模式，公共编程模式或特定专用测试模式中操作。 为了减少意外解码错误测试或编程模式的可能性，数据流具有足够大数量的N位，以显着降低错误解码的概率。 为了进一步降低意外解码编程或测试模式的可能性，如果在N位串行数据流的累积期间检测到少于或多于N个时钟，则可以复位特殊模式键匹配比较模块。 特殊模式键匹配数据模式可以表示正常的用户模式，公共编程模式和特定的私人制造商测试模式。

公开(公告)号：US20080147979A1

公开(公告)日：2008-06-19

申请号：US11928242

申请日：2007-10-30

申请人： Rodney J. Pesavento ,  Gregg D. Lahti ,  Joseph W. Triece

发明人： Rodney J. Pesavento ,  Gregg D. Lahti ,  Joseph W. Triece

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A cache module for a central processing unit has a cache control unit with an interface for a memory, a cache memory coupled with the control unit, wherein the cache memory has a plurality of cache lines, at least one cache line of the plurality of cache lines has an address tag bit field and an associated storage area for storing instructions or data, wherein the address tag bit field is readable and writeable and wherein the cache control unit is operable upon detecting that an address has been written to the address tag bit field to initiate a preload function in which instructions or data from the memory are loaded from the address into the at least one cache line.

摘要翻译： 一种用于中央处理单元的缓存模块具有一个具有用于存储器的接口的高速缓存控制单元，与控制单元耦合的高速缓冲存储器，其中高速缓冲存储器具有多条高速缓存行，多条高速缓存行中的至少一条高速缓存行 线路具有用于存储指令或数据的地址标签位字段和相关联的存储区域，其中地址标签位字段是可读写的，并且其中高速缓存控制单元在检测到地址已被写入地址标签位字段 以启动预载功能，其中来自存储器的指令或数据从地址加载到至少一个高速缓存行中。

公开(公告)号：US06563740B2

公开(公告)日：2003-05-13

申请号：US09951280

申请日：2001-09-13

申请人： Joseph A. Thomsen ,  Mitchel Obolsky ,  Joseph W. Triece

发明人： Joseph A. Thomsen ,  Mitchel Obolsky ,  Joseph W. Triece

IPC分类号： G11C1134

CPC分类号： G11C29/50004 ,  G11C16/04 ,  G11C16/3418 ,  G11C29/50

摘要： An electronic circuit includes a non-volatile memory on an integrated circuit that has several memory cells. The cells each have a voltage state and a gate. A gate bias circuit on the integrated circuit is coupled to the gates of the memory cells. The gate bias circuit includes at least a read voltage and a margin voltage. A detection circuit on the integrated circuit is coupled to the cells. The detection circuit includes a comparator and a reference voltage. The reference voltage and the voltage state of one of the cells are coupled to the comparator. The detection circuit includes an output generating a signal corresponding to the comparator output. The integrated circuit includes a monitor circuit. The monitor circuit is coupled to the output of the detection circuit and determines whether the voltage state of the cell transitions between application of the read and margin voltages to the gate.

公开(公告)号：US06230275B1

公开(公告)日：2001-05-08

申请号：US09232053

申请日：1999-01-15

申请人： Joseph W. Triece ,  Rodney Drake ,  Igor Wojewoda

发明人： Joseph W. Triece ,  Rodney Drake ,  Igor Wojewoda

IPC分类号： G06F126

CPC分类号： G11C5/14 ,  G11C7/1045 ,  H03K19/0016

摘要： A system for powering down configuration circuits to minimize power consumption has at least one first configuration circuit for configuring a peripheral module. A second configuration circuit is coupled to the peripheral module and to the at least one first configuration circuit. The second configuration circuit is used for enabling and disabling the peripheral module. The second configuration circuit is further used to power down the at least one first configuration circuit to minimize current consumption of the at least one first configuration circuit when the peripheral module is disabled.

摘要翻译： 用于断电配置电路以最小化功耗的系统具有用于配置外围模块的至少一个第一配置电路。 第二配置电路耦合到外围模块和至少一个第一配置电路。 第二个配置电路用于启用和禁用外围模块。 当外围模块被禁用时，第二配置电路还用于断电至少一个第一配置电路以最小化至少一个第一配置电路的电流消耗。

公开(公告)号：US5987583A

公开(公告)日：1999-11-16

申请号：US959942

申请日：1997-10-29

申请人： Joseph W. Triece ,  Sumit K. Mitra

发明人： Joseph W. Triece ,  Sumit K. Mitra

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/34 ,  G06F9/35 ,  G06F9/355

CPC分类号： G06F9/30181 ,  G06F9/30101 ,  G06F9/35

摘要： A system for allowing multiple addressing modes while maximizing a number of available opcodes and addressable registers. The system has a processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses. The system has an instruction set having a plurality of instructions. Each instruction has a plurality of bits wherein none of the plurality of bits in each of the plurality of instructions are dedicated bits for implementing different addressing modes. Each of the plurality of instructions are able to implement different addressing modes by addressing the virtual register addresses in the processor architecture scheme. Since no bits are required for implementing different addressing modes, the length of the opcode field and the register address field are determined by the number of opcodes and the number of addressable registers the user wishes to implement.

摘要翻译： 一种允许多个寻址模式同时最大化可用操作码和可寻址寄存器数量的系统。 该系统具有处理器架构方案，其允许通过使用虚拟寄存器地址对多个寻址模式进行编码。 该系统具有指令集，该指令集具有多个指令。 每个指令具有多个位，其中多个指令中的每一个中的多个位中的每一个都不是用于实现不同寻址模式的专用位。 多个指令中的每一个能够通过在处理器架构方案中寻址虚拟寄存器地址来实现不同的寻址模式。 由于不需要位来实现不同的寻址模式，所以操作码字段和寄存器地址字段的长度由操作码的数量和用户希望实现的可寻址寄存器的数量来确定。

公开(公告)号：US08825912B2

公开(公告)日：2014-09-02

申请号：US12564493

申请日：2009-09-22

申请人： Gregg Lahti ,  Rodney Pesavento ,  Joseph W. Triece ,  D. C. Sessions

发明人： Gregg Lahti ,  Rodney Pesavento ,  Joseph W. Triece ,  D. C. Sessions

IPC分类号： G06F3/00 ,  G06F13/28 ,  G06F13/12

CPC分类号： G06F13/124 ,  G06F13/28 ,  Y02D10/14

摘要： A microcontroller or integrated system has a bus, a plurality of peripheral devices each one coupled with the bus, a non-volatile memory, and a state machine coupled with the non-volatile memory and being operable to initialize the peripheral devices by reading initialization information from the non-volatile memory and writing it to the peripheral devices.

摘要翻译： 微控制器或集成系统具有总线，与总线耦合的多个外围设备，非易失性存储器和与非易失性存储器耦合的状态机，并且可操作以通过读取初始化信息来初始化外围设备 从非易失性存储器写入外围设备。