公开(公告)号：US20070284645A1

公开(公告)日：2007-12-13

申请号：US11799685

申请日：2007-05-02

申请人： Chang-Hyun Lee ,  Kyu-Charn Park

发明人： Chang-Hyun Lee ,  Kyu-Charn Park

IPC分类号： G11C7/00

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： A non-volatile memory device includes a substrate having a first region and a second region. A first gate electrode is disposed on the first region. A multi-layered charge storage layer is interposed between the first gate electrode and the substrate, the multi-layered charge storage including a tunnel insulation, a trap insulation, and a blocking insulation layer which are sequentially stacked. A second gate electrode is placed on the substrate of the second region, the second gate electrode including a lower gate and an upper gate connected to a region of an upper surface of the lower gate. A gate insulation layer is interposed between the second gate electrode and the substrate. The first gate electrode and the upper gate of the second gate electrode comprise a same material.

摘要翻译： 非易失性存储器件包括具有第一区域和第二区域的衬底。 第一栅电极设置在第一区域上。 在第一栅电极和基板之间插入多层电荷存储层，多层电荷存储包括依次堆叠的隧道绝缘，阱绝缘和阻挡绝缘层。 第二栅极被放置在第二区域的衬底上，第二栅极包括下栅极和连接到下栅极的上表面区域的上栅极。 栅极绝缘层介于第二栅电极和衬底之间。 第二栅电极的第一栅电极和上栅极包括相同的材料。

公开(公告)号：US06960500B2

公开(公告)日：2005-11-01

申请号：US10777233

申请日：2004-02-11

申请人： You-Cheol Shin ,  Kyu-Charn Park ,  Won-Hong Lee ,  Jung-Dal Choi

发明人： You-Cheol Shin ,  Kyu-Charn Park ,  Won-Hong Lee ,  Jung-Dal Choi

IPC分类号： H01L21/28 ,  H01L21/00 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/82 ,  H01L21/8238 ,  H01L21/8247 ,  H01L27/108 ,  H01L27/115 ,  H01L29/04 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.

摘要翻译： 一种半导体器件包括多个栅极线，其由在多个晶体管中用作栅电极的线形构成，并且通过栅极绝缘层与基板分离，各自具有上金属硅化物层; 以及仅通过进行杂质注入工艺而在所述栅极线之间的衬底上形成的多个源极/漏极区域。

公开(公告)号：US06903406B2

公开(公告)日：2005-06-07

申请号：US10346957

申请日：2003-01-17

申请人： Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

发明人： Chang-Hyun Lee ,  Kyu-Charn Park ,  Jeong-Hyuk Choi ,  Sung-Hoi Hur

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  Y10S257/905

摘要： This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers. The method for forming the self-aligned floating gate and the control gate electrode includes forming trenches in a semiconductor substrate to define a plurality of active regions and concurrently forming an oxide layer pattern, a floating gate pattern, a dielectric layer pattern and a control gate pattern that are sequentially stacked. A conductive layer is then formed on the device isolation layers and the control gate pattern. Thereafter, the conductive layer, the control gate pattern, the dielectric layer pattern, the floating gate pattern, and the oxide layer pattern are successively patterned.

摘要翻译： 本公开提供具有浮动栅极的非易失性存储器件单元以及用于制造其的方法。 非易失性存储器件的单元包括在限定多个有源区域的半导体衬底的预定区域上彼此并联的器件隔离层。 每个器件隔离层具有突出在半导体衬底上的侧壁。 多个字线跨越器件隔离层。 隧道氧化物层，浮置栅极，栅极层间电介质层和控制栅极电极顺序堆叠在每个有源区域和每条字线之间。 浮栅和控制栅极具有与相邻器件隔离层自对准的侧壁。 形成自对准浮栅和控制栅极的方法包括在半导体衬底中形成沟槽以限定多个有源区并同时形成氧化物层图案，浮栅图案，电介质层图案和控制栅极 顺序堆叠的图案。 然后在器件隔离层和控制栅极图案上形成导电层。 此后，连续地形成导电层，控制栅极图案，电介质层图案，浮栅图案和氧化物层图案。

公开(公告)号：US06797570B2

公开(公告)日：2004-09-28

申请号：US10087330

申请日：2002-03-01

申请人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur

发明人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Heung-Kwun Oh ,  Sung-Hoi Hur

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

摘要翻译： 提供了NAND​​型闪存器件及其制造方法。 NAND型闪速存储器件包括彼此平行延伸的多个隔离层，它们形成在半导体衬底的预定区域。 该装置还包括串联选择线图案，多个字线图案和跨越隔离层和隔离层之间的有源区域的接地选择线图案。 源极区域形成在与地选择线图案相邻的有源区域中并且与串选择线图案相反。 源极区域和源极区域之间的隔离层被与地选择线图案平行延伸的公共源极线覆盖。

公开(公告)号：US06720579B2

公开(公告)日：2004-04-13

申请号：US10041732

申请日：2002-01-07

申请人： You-Cheol Shin ,  Kyu-Charn Park ,  Won-Hong Lee ,  Jung-Dal Choi

发明人： You-Cheol Shin ,  Kyu-Charn Park ,  Won-Hong Lee ,  Jung-Dal Choi

IPC分类号： H01L27108

CPC分类号： H01L27/11521 ,  H01L27/115

摘要： A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.

摘要翻译： 一种半导体器件包括多个栅极线，其由在多个晶体管中用作栅电极的线形构成，并且通过栅极绝缘层与基板分离，各自具有上金属硅化物层; 以及仅通过进行杂质注入工艺而在所述栅极线之间的衬底上形成的多个源极/漏极区域。

公开(公告)号：US06624464B2

公开(公告)日：2003-09-23

申请号：US10001460

申请日：2001-10-29

申请人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Sung-Nam Chang ,  Jung-Dal Choi ,  Won-Hong Lee

发明人： Kwang-Shik Shin ,  Kyu-Charn Park ,  Sung-Nam Chang ,  Jung-Dal Choi ,  Won-Hong Lee

IPC分类号： H01L2976

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11524

摘要： A non-volatile memory cell array having second floating gates with a narrow width, a large height, and slanted side walls. Critical dimension errors due to photolithographic and etching processes are decreased. The difference in the coupling ratio between the memory cells is low thereby improving speed during programming and/or erasing. A second floating gate having a narrower critical dimension than a second floating gate obtained using a photolithographic process may be designed, thereby forming a highly integrated non-volatile memory cell array.

公开(公告)号：US06521941B2

公开(公告)日：2003-02-18

申请号：US09861213

申请日：2001-05-17

申请人： Kyu-Charn Park ,  Jung-Dal Choi ,  Yong-Sik Yim

发明人： Kyu-Charn Park ,  Jung-Dal Choi ,  Yong-Sik Yim

IPC分类号： H01L29788

CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11531 ,  H01L29/42324 ,  H01L29/511

摘要： A non-volatile memory device and fabrication methods thereof are provided. A first inter-gate insulating layer is formed to intervene between control gate electrodes and floating gate electrodes in a cell array area. A second inter-gate insulating layer is formed to intervene between a gate electrode and a dummy gate electrode in a peripheral circuit area. The second inter-gate insulating layer has a thickness greater than a thickness of the first inter-gate insulating layer on a top surface of the floating gate electrodes. By reducing the difference between the thickness of the first inter-gate insulating layer on sidewalls of floating gate patterns and the thickness of the second inter-gate insulating layer on a gate electrode pattern, in accordance with the invention, any etching damage to the substrate in the peripheral circuit area can be considerably reduced or prevented during the fabrication process.

摘要翻译： 提供一种非易失性存储器件及其制造方法。 形成第一栅极间绝缘层，以在单元阵列区域中的控制栅极电极和浮动栅极电极之间插入。 形成第二栅极间绝缘层，以在外围电路区域中的栅电极和伪栅电极之间插入。 所述第二栅极间绝缘层的厚度大于所述浮置栅电极的顶面上的所述第一栅极间绝缘层的厚度。 通过减小浮置栅极图案的侧壁上的第一栅极间绝缘层的厚度与栅极电极图案上的第二栅极间绝缘层的厚度之间的差异，根据本发明，对衬底的任何蚀刻损伤 在制造过程中可以显着地减少或防止在外围电路区域中。