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    Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby
    1.
    发明授权
    Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby 有权
    制造具有多栅极绝缘层的半导体器件和由此制造的半导体器件的方法

    公开(公告)号：US07508048B2

    公开(公告)日：2009-03-24

    申请号：US10758802

    申请日：2004-01-15

    申请人： Dae-Woong Kang ,  Hong-Soo Kim ,  Jung-Dal Choi ,  Kyu-Charn Park ,  Seong-Soon Cho ,  Yong-Sik Yim ,  Sung-Nam Chang

    发明人： Dae-Woong Kang ,  Hong-Soo Kim ,  Jung-Dal Choi ,  Kyu-Charn Park ,  Seong-Soon Cho ,  Yong-Sik Yim ,  Sung-Nam Chang

    IPC分类号： H01L29/00

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11543

    摘要： Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby are provided. The method includes forming a pad insulation layer and an initial high voltage gate insulation layer on a first region and a second region of a semiconductor substrate respectively. The initial high voltage gate insulation layer is formed to be thicker than the pad insulation layer. A first isolation layer that penetrates the pad insulation layer and is buried in the semiconductor substrate is formed to define a first active region in the first region, and a second isolation layer that penetrates the initial high voltage gate insulation layer and is buried in the semiconductor substrate is formed to define a second active region in the second region. The pad insulation layer is then removed to expose the first active region. A low voltage gate insulation layer is formed on the exposed first active region. Accordingly, it can minimize a depth of recessed regions (dent regions) to be formed at edge regions of the first isolation layer during removal of the pad insulation layer, and it can prevent dent regions from being formed at edge regions of the second isolation layer.

    摘要翻译： 提供了制造具有多栅极绝缘层的半导体器件和由此制造的半导体器件的方法。 该方法包括分别在半导体衬底的第一区域和第二区域上形成衬垫绝缘层和初始高电压栅极绝缘层。 初始高压栅绝缘层形成为比焊垫绝缘层厚。 形成穿过焊盘绝缘层并被埋在半导体衬底中的第一隔离层，以限定第一区域中的第一有源区和穿过初始高电压栅极绝缘层并被埋在半导体中的第二隔离层 形成衬底以限定第二区域中的第二有源区。 然后去除焊盘绝缘层以露出第一有源区。 在暴露的第一有源区上形成低压栅极绝缘层。 因此，能够最大限度地减少在去除焊盘绝缘层期间在第一隔离层的边缘区域形成的凹陷区域（凹陷区域）的深度，并且可以防止凹陷区域形成在第二隔离层的边缘区域 。

    Non-volatile memory device and fabrication method thereof
    2.
    发明授权
    Non-volatile memory device and fabrication method thereof 有权
    非易失性存储器件及其制造方法

    公开(公告)号：US06521941B2

    公开(公告)日：2003-02-18

    申请号：US09861213

    申请日：2001-05-17

    申请人： Kyu-Charn Park ,  Jung-Dal Choi ,  Yong-Sik Yim

    发明人： Kyu-Charn Park ,  Jung-Dal Choi ,  Yong-Sik Yim

    IPC分类号： H01L29788

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11531 ,  H01L29/42324 ,  H01L29/511

    摘要： A non-volatile memory device and fabrication methods thereof are provided. A first inter-gate insulating layer is formed to intervene between control gate electrodes and floating gate electrodes in a cell array area. A second inter-gate insulating layer is formed to intervene between a gate electrode and a dummy gate electrode in a peripheral circuit area. The second inter-gate insulating layer has a thickness greater than a thickness of the first inter-gate insulating layer on a top surface of the floating gate electrodes. By reducing the difference between the thickness of the first inter-gate insulating layer on sidewalls of floating gate patterns and the thickness of the second inter-gate insulating layer on a gate electrode pattern, in accordance with the invention, any etching damage to the substrate in the peripheral circuit area can be considerably reduced or prevented during the fabrication process.

    摘要翻译： 提供一种非易失性存储器件及其制造方法。 形成第一栅极间绝缘层，以在单元阵列区域中的控制栅极电极和浮动栅极电极之间插入。 形成第二栅极间绝缘层，以在外围电路区域中的栅电极和伪栅电极之间插入。 所述第二栅极间绝缘层的厚度大于所述浮置栅电极的顶面上的所述第一栅极间绝缘层的厚度。 通过减小浮置栅极图案的侧壁上的第一栅极间绝缘层的厚度与栅极电极图案上的第二栅极间绝缘层的厚度之间的差异，根据本发明，对衬底的任何蚀刻损伤 在制造过程中可以显着地减少或防止在外围电路区域中。

    Non-volatile memory device having a metal-oxide-nitride-oxide-semiconductor gate structure
    3.
    发明授权
    Non-volatile memory device having a metal-oxide-nitride-oxide-semiconductor gate structure 有权
    具有金属氧化物 - 氮化物 - 氧化物半导体栅极结构的非易失性存储器件

    公开(公告)号：US06750525B2

    公开(公告)日：2004-06-15

    申请号：US10099581

    申请日：2002-03-15

    申请人： Yong-Sik Yim ,  Jung-Dal Choi ,  Hong-Suk Kwack ,  You-Cheol Shin

    发明人： Yong-Sik Yim ,  Jung-Dal Choi ,  Hong-Suk Kwack ,  You-Cheol Shin

    IPC分类号： H01L2900

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L29/792

    摘要： A non-volatile memory device having a MONOS (Metal-oxide-nitride-oxide-semiconductor) gate structure is provided. This device includes a selection transistor and a cell transistor including a cell gate insulation layer formed in a cell array area and a low-voltage MOS transistor having a low-voltage gate insulation layer and a high-voltage MOS transistor having a high-voltage gate insulation layer formed in a peripheral circuit area. The low-voltage gate insulation layer is thinner than the high-voltage gate insulation layer. The low-voltage gate insulation layer can also be thinner than the equivalent thickness of the cell gate insulation layer.

    摘要翻译： 提供具有MONOS（金属氧化物 - 氮化物 - 氧化物半导体）栅极结构的非易失性存储器件。 该器件包括选择晶体管和包括形成在单元阵列区域中的单元栅极绝缘层和具有低压栅极绝缘层的低压MOS晶体管和具有高压栅极的高压MOS晶体管的单元晶体管 绝缘层形成在外围电路区域中。 低压栅极绝缘层比高压栅极绝缘层薄。 低压栅极绝缘层也可以比单元栅极绝缘层的等效厚度薄。

    Nand-type flash memory device and method of forming the same
    4.
    发明授权
    Nand-type flash memory device and method of forming the same 失效
    Nand型闪存器件及其形成方法

    公开(公告)号：US06576513B2

    公开(公告)日：2003-06-10

    申请号：US10272972

    申请日：2002-10-16

    申请人： Yong-Sik Yim ,  Jung-Dal Choi

    发明人： Yong-Sik Yim ,  Jung-Dal Choi

    IPC分类号： H01L218247

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A NAND-type flash memory device for preventing punchthrough and a method for forming the same are provided. The NAND-type flash memory device includes a string selection transistor, a plurality of cell memory transistors, and a ground selection transistor being sequentially connected in series. The device further includes a bitline contact connected to a drain region of the string selection transistor, and a common source line connected to a source region of the ground selection transistor. Impurities are heavily doped to a drain-to-channel interface in the string selection transistor and a channel-to-source interface in the ground selection transistor, forming pockets for preventing punchthrough. The pockets are preferably formed using a tilted ion implantation using the vertical gate structures as masks.

    摘要翻译： 提供了一种用于防止穿透的NAND型闪存器件及其形成方法。 NAND型闪速存储器件包括串联选择晶体管，多个单元存储晶体管和接地选择晶体管，其串联连接。 该器件还包括连接到串选择晶体管的漏极区的位线接点和连接到接地选择晶体管的源极区的公共源极线。 杂质被重掺杂到串选择晶体管中的漏极至沟道界面以及接地选择晶体管中的沟道到源极接口，形成用于防止穿透的凹穴。 凹穴优选使用垂直栅极结构作为掩模使用倾斜离子注入形成。

    Method of forming a non-volatile memory device having a metal-oxide-nitride-oxide-semiconductor gate structure
    5.
    发明授权
    Method of forming a non-volatile memory device having a metal-oxide-nitride-oxide-semiconductor gate structure 有权
    形成具有金属氧化物 - 氮化物 - 氧化物 - 半导体栅极结构的非易失性存储器件的方法

    公开(公告)号：US06734065B2

    公开(公告)日：2004-05-11

    申请号：US10418848

    申请日：2003-04-18

    申请人： Yong-Sik Yim ,  Jung-Dal Choi ,  Hong-Suk Kwack ,  You-Cheol Shin

    发明人： Yong-Sik Yim ,  Jung-Dal Choi ,  Hong-Suk Kwack ,  You-Cheol Shin

    IPC分类号： H01L21336

    CPC分类号： H01L27/11526 ,  H01L27/105 ,  H01L27/11529 ,  H01L29/792

    摘要： Embodiments of the invention provide a method that includes forming a selection transistor and a cell transistor that includes a cell gate insulation layer in a cell array area. The method also includes forming a low-voltage MOS transistor having a low-voltage gate insulation layer and a high-voltage MOS transistor having a high-voltage gate insulation layer in a peripheral circuit area. The low-voltage gate insulation layer is formed thinner than the high-voltage gate insulation layer. The low voltage gate insulation layer may also be formed thinner than the equivalent thickness of the cell gate insulation layer.

    摘要翻译： 本发明的实施例提供了一种方法，其包括在单元阵列区域中形成选择晶体管和包括单元栅极绝缘层的单元晶体管。 该方法还包括在外围电路区域中形成具有低电压栅极绝缘层的低压MOS晶体管和具有高电压栅极绝缘层的高压MOS晶体管。 低压栅极绝缘层的形成比高压栅极绝缘层薄。 低压栅极绝缘层也可以形成为比单元栅极绝缘层的等效厚度更薄。

    Floating trap-type non-volatile memory device
    6.
    发明授权
    Floating trap-type non-volatile memory device 失效
    浮动陷阱型非易失性存储器件

    公开(公告)号：US06753572B2

    公开(公告)日：2004-06-22

    申请号：US10189075

    申请日：2002-07-02

    申请人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Yong-Sik Yim

    发明人： Chang-Hyun Lee ,  Jung-Dal Choi ,  Yong-Sik Yim

    IPC分类号： H01L29792

    CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L21/28282 ,  H01L29/518 ,  H01L29/792

    摘要： A floating trap type non-volatile memory device and fabrication method thereof are provided. The floating trap type device comprises a substrate, a gate electrode formed on the substrate. A charge storage layer is interposed between the substrate and the gate electrode. A tunneling layer is interposed between the substrate and charge storage layer. The charge storage layer comprises a material having a narrower band gap than silicon nitride. The charge storage layer preferably formed of tetrahedral amorphous carbon. The potential barrier between the charge storage layer and the tunneling layer is increased by using the tetrahedral amorphous carbon as the charge storage layer. Therefore, the charge retention characteristic of the floating trap type device is improved.

    摘要翻译： 提供了一种浮动阱型非易失性存储器件及其制造方法。 浮动阱型器件包括衬底，形成在衬底上的栅电极。 电荷存储层介于基板和栅电极之间。 在衬底和电荷存储层之间插入隧穿层。 电荷存储层包括具有比氮化硅更窄的带隙的材料。 电荷存储层优选由四面体无定形碳形成。 通过使用四面体非晶碳作为电荷存储层，电荷存储层与隧道层之间的势垒增加。 因此，浮动捕获型装置的电荷保持特性得到改善。

    NAND-type flash memory device and method of forming the same
    7.
    发明授权
    NAND-type flash memory device and method of forming the same 失效

    公开(公告)号：US06567308B2

    公开(公告)日：2003-05-20

    申请号：US09965532

    申请日：2001-09-26

    申请人： Yong-Sik Yim ,  Jung-Dal Choi

    发明人： Yong-Sik Yim ,  Jung-Dal Choi

    IPC分类号： H01L218247

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A NAND-type flash memory device for preventing punchthrough and a method for forming the same are provided. The NAND-type flash memory device includes a string selection transistor, a plurality of cell memory transistors, and a ground selection transistor being sequentially connected in series. The device further includes a bitline contact connected to a drain region of the string selection transistor, and a common source line connected to a source region of the ground selection transistor. Impurities are heavily doped to a drain-to-channel interface in the string selection transistor and a channel-to-source interface in the ground selection transistor, forming pockets for preventing punchthrough. The pockets are preferably formed using a tilted ion implantation using the vertical gate structures as masks.

    Semiconductor devices having a convex active region and methods of forming the same
    8.
    发明申请
    Semiconductor devices having a convex active region and methods of forming the same 有权
    具有凸起的有源区的半导体器件及其形成方法

    公开(公告)号：US20080057644A1

    公开(公告)日：2008-03-06

    申请号：US11642198

    申请日：2006-12-20

    申请人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

    发明人： Dong-Hwa Kwak ,  Jae-Kwan Park ,  Yong-Sik Yim ,  Won-Cheol Jeong ,  Jae-Hwang Sim

    IPC分类号： H01L21/336

    CPC分类号： H01L27/105 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

    摘要： Methods of forming a semiconductor device include forming a trench mask pattern on a semiconductor substrate having active regions and device isolation regions. A thermal oxidation process is performed using the trench mask pattern as a diffusion mask to form a thermal oxide layer defining a convex upper surface of the active regions. The thermal oxide layer and the semiconductor substrate are etched using the trench mask pattern as an etch mask to form trenches defining convex upper surfaces of the active regions. The trench mask pattern is removed to expose the convex upper surfaces of the active regions. Gate patterns are formed extending over the active regions.

    摘要翻译： 形成半导体器件的方法包括在具有有源区和器件隔离区的半导体衬底上形成沟槽掩模图案。 使用沟槽掩模图案作为扩散掩模进行热氧化处理，以形成限定有源区的凸上表面的热氧化层。 使用沟槽掩模图案作为蚀刻掩模蚀刻热氧化物层和半导体衬底，以形成限定有源区的凸上表面的沟槽。 去除沟槽掩模图案以露出活性区域的凸上表面。 形成在有源区域上延伸的栅极图案。