公开(公告)号：US6025752A

公开(公告)日：2000-02-15

申请号：US087924

申请日：1998-06-01

Applicant: Changming Zhou ,  Guoliang Shou ,  Shengmin Lin ,  Takashi Tomatsu ,  Jie Chen

Inventor： Changming Zhou ,  Guoliang Shou ,  Shengmin Lin ,  Takashi Tomatsu ,  Jie Chen

IPC: H03F1/30 ,  H03F3/00 ,  H03F1/14

CPC classification number: H03F1/303 ,  H03F3/005

Abstract: An inverting amplifying circuit for outputting an inversion of an input with good linearity, having an inverter circuit, a feedback capacitance, an input capacitance, a first refresh switch, a second refresh switch, a sleep switch, and a first cutoff switch. A sleep voltage is input through the sleep switch to the inverter circuit for minimizing the electrical power consumption. The sleep switch connects a terminal of the inverter circuit directly to ground when in a sleep mode. The first cut off switch is connected between an output of the inverter circuit and an output of the inverting amplifying circuit.

Abstract translation: 一种用于输出具有良好线性度的输入的反相的反相放大电路，具有反相器电路，反馈电容，输入电容，第一刷新开关，第二刷新开关，休眠开关和第一截止开关。 睡眠电压通过睡眠开关输入到逆变器电路，以最小化电力消耗。 休眠开关在休眠模式下将逆变器电路的端子直接连接到地。 第一截止开关连接在逆变器电路的输出端和反相放大电路的输出端之间。

公开(公告)号：US5945875A

公开(公告)日：1999-08-31

申请号：US47457

申请日：1998-03-25

Applicant: Xuping Zhou ,  Guoliang Shou ,  Changming Zhou

Inventor： Xuping Zhou ,  Guoliang Shou ,  Changming Zhou

IPC: H04L27/22 ,  H04L27/233 ,  H03D3/00

CPC classification number: H04L27/2331

Abstract: A .pi./n shift PSK demodulator of this invention is formed with a digital logical means through the following method. XOR4 calculates the ex-OR operation between the present sample through .pi./4 shift QPSK output from SH2 and the previous one output from SH1. Accumulating 1 among the outputs from XOR4 in the first operation means 5 and multiplying it by .pi./8 obtains the absolute phase difference between the present and the previous symbols. The former or latter four bits from SH1 are subtracted from the corresponding former or latter four bits from SH2, and the result of each bit is summed and its sign is added to the absolute phase data in sign addition means 10. After the phase offset is subtracted from the outputs from 10, it is demodulated into the original one in judgment circuit 13.

Abstract translation: 本发明的π/ n移位PSK解调器通过以下方法由数字逻辑装置形成。 XOR4通过从SH2输出的pi / 4移位QPSK和SH1的前一个输出来计算当前采样之间的异或运算。 在第一操作装置5中从XOR4的输出中累积1，并将其乘以pi / 8获得当前和先前符号之间的绝对相位差。 来自SH1的前者或后者的四位从SH2的相应的前一个或后四位中减去，每个位的结果被相加，并且其符号被加到符号加法装置10中的绝对相位数据。在相位偏移为 从10的输出中减去，在判断电路13中被解调成原来的。

公开(公告)号：US5848096A

公开(公告)日：1998-12-08

申请号：US708987

申请日：1996-09-06

Applicant: Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Mamoru Sawahashi ,  Fumiyuki Adachi ,  Sunao Takatori

Inventor： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Mamoru Sawahashi ,  Fumiyuki Adachi ,  Sunao Takatori

IPC: H04J13/00 ,  H04B1/707 ,  H04J13/16 ,  H04K1/02

CPC classification number: H04B1/707 ,  H04B1/7093

Abstract: A communication method and system which can enlarge the communication capacity using a rather simple system. The communication method and system provides different spreading codes to two signal systems at a receiving station.

Abstract translation: 一种可以使用相当简单的系统来扩大通信容量的通信方法和系统。 通信方法和系统在接收站向两个信号系统提供不同的扩展码。

公开(公告)号：US5844937A

公开(公告)日：1998-12-01

申请号：US744954

申请日：1996-11-07

Applicant: Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Kenzo Urabe ,  Sunao Takatori

Inventor： Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Kenzo Urabe ,  Sunao Takatori

IPC: H03H15/00 ,  H03H11/04 ,  H03H17/02 ,  H04B1/7093 ,  H04J13/00 ,  H04B15/00

CPC classification number: H04B1/7093 ,  H03H11/04 ,  H03H17/0254

Abstract: The present invention solves the conventional problems and has an object to provide a matched filter system of high process in speed, a small size and low electric power consumption. The matched filter circuits of each matched filter set is allocated different n combinations of M/n digits selected from the M length PN code sequence picking one out of every n digits, cyclically performs sampling every 1 chip time duration the input signals to be inputted to each set constructed by matched filter circuits by n sets each of which including n matched filter circuits, and calculates the sum of outputs of all matched filter circuits.

Abstract translation: 本发明解决了以往的问题，其目的在于提供一种速度快，体积小，功耗低的匹配滤波系统。 每个匹配滤波器组的匹配滤波器电路被分配从从n个数字中选出一个的M个长度PN码序列中选择的M / n个数字的不同n个组合，每1个码片持续时间周期地执行要输入的输入信号的采样 每组由匹配滤波器电路构成，每组包括n个匹配滤波器电路，并且计算所有匹配滤波器电路的输出之和。

公开(公告)号：US5812546A

公开(公告)日：1998-09-22

申请号：US802635

申请日：1997-02-19

Applicant: Changming Zhou ,  Guoliang Shou ,  Xuping Zhou ,  Makoto Yamamoto ,  Kenzo Urabe ,  Sunao Takatori

Inventor： Changming Zhou ,  Guoliang Shou ,  Xuping Zhou ,  Makoto Yamamoto ,  Kenzo Urabe ,  Sunao Takatori

IPC: H04B1/707 ,  H04B1/7093 ,  H04J13/04

CPC classification number: H04B1/7093

Abstract: The demodulator has a plurality of matched filters in parallel. Each matched filter has a different binary PN code, a plurality of sample holders, a plurality of multipliers, an adder, and a controller. The sample holders has a common input, a switch, a first capacitor, a first inverse amplifier with an output and an input connected to the common input through the switch and the capacitor, and a first feedback capacitor for feeding the output of the first inverse amplifier back to the input. Each multiplier has a first and second sub-multiplexers, one of sub-multiplexer selecting corresponding sample holder output and another sub-multiplexer selecting a reference voltage.

Abstract translation: 解调器具有并联的多个匹配滤波器。 每个匹配滤波器具有不同的二进制PN码，多个采样保持器，多个乘法器，加法器和控制器。 样本保持器具有公共输入，开关，第一电容器，具有输出的第一反相放大器和通过开关和电容器连接到公共输入的输入端，以及用于馈送第一反相器的输出的第一反馈电容器 放大器返回输入。 每个乘法器具有第一和第二子复用器，其中一个子复用器选择对应的采样保持器输出，另一个副多路复用器选择参考电压。

公开(公告)号：US5781584A

公开(公告)日：1998-07-14

申请号：US689143

申请日：1996-07-30

Applicant: Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Sunao Takatori

Inventor： Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Sunao Takatori

IPC: H03H17/02 ,  H03H11/04 ,  H04B1/709 ,  H04J13/00 ,  H04L7/00 ,  H04L7/10 ,  H04B1/707

CPC classification number: H04B1/708 ,  H04B1/7085 ,  H04B1/7093 ,  H04B1/7095 ,  H04B2201/70709

Abstract: A filter circuit largely reducing electric power consumption compared with a conventional one, as well as realizing the initial acquisition in high enough speed. In a filter circuit according to the present invention, a matched filter and a sliding correlator are used in parallel; the first acquisition and holding is executed by a matched filter, a correlating operation is executed by a sliding correlator and a voltage supply to the matched filter is stopped.

Abstract translation: 与现有技术相比，大大降低电力消耗的滤波电路，以及以足够高的速度实现初始采集。 在根据本发明的滤波器电路中，并行使用匹配滤波器和滑动相关器， 通过匹配滤波器执行第一采集和保持，通过滑动相关器执行相关操作，并且停止对匹配滤波器的电压供应。

公开(公告)号：US5751624A

公开(公告)日：1998-05-12

申请号：US715732

申请日：1996-09-19

Applicant: Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Sunao Takatori

Inventor： Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Sunao Takatori

IPC: G06G7/22 ,  G06J1/00 ,  G06C15/08

CPC classification number: G06G7/22 ,  G06J1/00

Abstract: A complex number calculation circuit for directly multiplying a complex number of an analog signal by a digital complex number as a multiplier. A capacitive coupling is used with a plurality of parallel capacitances corresponding to weights of bits of real and imaginary parts of the multiplier. The sign of the multiplier is represented by selection of output paths. A complex number calculation circuit for calculating approximated absolute values is suitable for an analog architecture. Inverter circuits are used for linear inversion of analog values, and capacitive couplings are used for weighted addition. Analog maximum and minimum circuits with parallel MOSs are used for maximum and minimum calculation.

Abstract translation: 一种用于将复数个模拟信号乘以数字复数作为乘数的复数计算电路。 电容耦合用于与乘法器的实部和虚部的位的权重相对应的多个并联电容。 乘法器的符号由输出路径的选择表示。 用于计算近似绝对值的复数计算电路适用于模拟架构。 逆变电路用于模拟值的线性反演，电容耦合用于加权相加。 具有并联MOS的模拟最大和最小电路用于最大和最小计算。