公开(公告)号：US5930290A

公开(公告)日：1999-07-27

申请号：US841217

申请日：1997-04-30

申请人： Changming Zhou ,  Guoliang Shou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Kenzo Urabe

发明人： Changming Zhou ,  Guoliang Shou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Kenzo Urabe

IPC分类号： H04B1/707 ,  H04B1/7093 ,  H04J13/10 ,  H04B15/00 ,  H04B7/216

CPC分类号： H04J13/0077 ,  H04B1/7093

摘要： A fast spread spectrum communication system is provided, having fewer circuits and requiring fewer PN codes to be assigned to a user. A series of digital data to be transmitted, is divided into 4-bit frames. The 4-bit data of each frame is divided into the first through fourth elements in a predetermined order. The first complex number is constructed by the first and second elements, and the second complex number is determined according to the value of the third and fourth elements. The spectrum of the data to be transmitted is spread by multiplying these complex numbers. Four matched filters despread a received signal by different combinations of PN codes stored in a receiver. The first through fourth elements are recovered according to the outputs of the matched filters.

摘要翻译： 提供了一种快速扩频通信系统，具有较少的电路并且需要较少的PN码来分配给用户。 要发送的一系列数字数据被分为4位帧。 每帧的4位数据按预定顺序分成第一至第四元素。 第一复数由第一和第二元素构成，第二复数根据第三和第四元素的值确定。 要传输的数据的频谱通过乘以这些复数来传播。 四个匹配滤波器通过存储在接收机中的PN码的不同组合对接收信号进行解扩。 根据匹配滤波器的输出，恢复第一至第四元件。

公开(公告)号：US5844937A

公开(公告)日：1998-12-01

申请号：US744954

申请日：1996-11-07

申请人： Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Kenzo Urabe ,  Sunao Takatori

发明人： Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Kenzo Urabe ,  Sunao Takatori

IPC分类号： H03H15/00 ,  H03H11/04 ,  H03H17/02 ,  H04B1/7093 ,  H04J13/00 ,  H04B15/00

CPC分类号： H04B1/7093 ,  H03H11/04 ,  H03H17/0254

摘要： The present invention solves the conventional problems and has an object to provide a matched filter system of high process in speed, a small size and low electric power consumption. The matched filter circuits of each matched filter set is allocated different n combinations of M/n digits selected from the M length PN code sequence picking one out of every n digits, cyclically performs sampling every 1 chip time duration the input signals to be inputted to each set constructed by matched filter circuits by n sets each of which including n matched filter circuits, and calculates the sum of outputs of all matched filter circuits.

摘要翻译： 本发明解决了以往的问题，其目的在于提供一种速度快，体积小，功耗低的匹配滤波系统。 每个匹配滤波器组的匹配滤波器电路被分配从从n个数字中选出一个的M个长度PN码序列中选择的M / n个数字的不同n个组合，每1个码片持续时间周期地执行要输入的输入信号的采样 每组由匹配滤波器电路构成，每组包括n个匹配滤波器电路，并且计算所有匹配滤波器电路的输出之和。

公开(公告)号：US5812546A

公开(公告)日：1998-09-22

申请号：US802635

申请日：1997-02-19

申请人： Changming Zhou ,  Guoliang Shou ,  Xuping Zhou ,  Makoto Yamamoto ,  Kenzo Urabe ,  Sunao Takatori

发明人： Changming Zhou ,  Guoliang Shou ,  Xuping Zhou ,  Makoto Yamamoto ,  Kenzo Urabe ,  Sunao Takatori

IPC分类号： H04B1/707 ,  H04B1/7093 ,  H04J13/04

CPC分类号： H04B1/7093

摘要： The demodulator has a plurality of matched filters in parallel. Each matched filter has a different binary PN code, a plurality of sample holders, a plurality of multipliers, an adder, and a controller. The sample holders has a common input, a switch, a first capacitor, a first inverse amplifier with an output and an input connected to the common input through the switch and the capacitor, and a first feedback capacitor for feeding the output of the first inverse amplifier back to the input. Each multiplier has a first and second sub-multiplexers, one of sub-multiplexer selecting corresponding sample holder output and another sub-multiplexer selecting a reference voltage.

摘要翻译： 解调器具有并联的多个匹配滤波器。 每个匹配滤波器具有不同的二进制PN码，多个采样保持器，多个乘法器，加法器和控制器。 样本保持器具有公共输入，开关，第一电容器，具有输出的第一反相放大器和通过开关和电容器连接到公共输入的输入端，以及用于馈送第一反相器的输出的第一反馈电容器 放大器返回输入。 每个乘法器具有第一和第二子复用器，其中一个子复用器选择对应的采样保持器输出，另一个副多路复用器选择参考电压。

公开(公告)号：US5974038A

公开(公告)日：1999-10-26

申请号：US864784

申请日：1997-05-29

申请人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori

发明人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori

IPC分类号： H04B1/707 ,  H04B1/7075 ,  H04B1/7093 ,  H04B1/7115 ,  H04L7/00 ,  H04B7/216

CPC分类号： H04B1/708 ,  H04B1/7093 ,  H04B1/7115 ,  H04B2201/70709

摘要： This invention reduces electric power consumption of a CDMA communication system receiver while it is in the wait mode. A received spread spectrum signal is demodulated in multiplication means into baseband signals Ri and Rq, and inputted into a complex matched filter. This filter is intermittently driven by supply voltage control means to perform acquisition of received signals. When an electric power calculation circuit detects the output of the filter to reach a peak equal to or greater than a predetermined value, the received signals undergo acquisition by controlling n number of correlators 26-1 to 26-n to work by a correlator controlling circuit. Moreover, de-spreading is performed. The outputs from each correlator 46-1 to 26-n are given to a RAKE combiner and demodulated by the RAKE by a combining and demodulating circuit.

摘要翻译： 本发明在CDMA通信系统接收机处于等待模式时降低电力消耗。 接收的扩频信号在乘法装置中被解调为基带信号Ri和Rq，并输入到复匹配滤波器中。 该滤波器由电源电压控制装置间歇地驱动，以执行接收信号的采集。 当电力计算电路检测到滤波器的输出达到等于或大于预定值的峰值时，通过控制n个相关器26-1至26-n来由相关器控制电路工作来接收接收的信号 。 此外，进行解扩。 来自每个相关器46-1至26-n的输出被提供给RAKE组合器，并由RAKE通过组合和解调电路进行解调。

公开(公告)号：US5872466A

公开(公告)日：1999-02-16

申请号：US686950

申请日：1996-07-26

申请人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori

发明人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori

IPC分类号： H03H11/04 ,  H03H17/02 ,  H04B1/707 ,  H04B1/7093 ,  H04L7/00 ,  H04L7/10 ,  H03K5/00

CPC分类号： H03H11/04 ,  H03H17/0254

摘要： A matched filter with reduced electric power consumption is disclosed. The matched filter circuit power consumption is reduced by stopping the electric power supply to an unnecessary circuit since input signal is partially sampled just after an acquisition. Since the spreading code is 1 bit data string, the input signal sampled and held is branched out into the signal groups "1" and "-1" by a multiplexer. The signals in each groups are added in parallel by a capacitive coupling, and the electric power is supplied in the circuit intermittently.

摘要翻译： 公开了具有降低的电力消耗的匹配滤波器。 由于输入信号在采集之后被部分采样，因此通过停止对不必要的电路的电力来降低匹配滤波器电路的功耗。 由于扩展码是1位数据串，采样和保持的输入信号通过多路复用器分支到信号组“1”和“-1”。 各组中的信号通过电容耦合并联并且在电路中间歇地供电。

公开(公告)号：US5783961A

公开(公告)日：1998-07-21

申请号：US764637

申请日：1996-12-11

申请人： Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Sunao Takatori

发明人： Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Sunao Takatori

IPC分类号： H03K19/0948 ,  H03F1/02 ,  H03F1/34 ,  H03F3/46 ,  H03F3/72 ,  H03K5/153 ,  H03H11/26

CPC分类号： H03F3/72

摘要： The present invention has an object to provide an inverted amplifying circuit with improved accuracy of output and reduced electric power consumption. In an inverted amplifying circuit according to the present invention, a MOS switch is connected between pMOS and nMOS of a CMOS inverter and between balancing resistances. The MOS switch is opened when the inverted amplifying circuit does not work.

摘要翻译： 本发明的目的是提供一种具有提高的输出精度和降低的电力消耗的反相放大电路。 在根据本发明的反相放大电路中，MOS开关连接在CMOS反相器的pMOS和nMOS之间以及平衡电阻之间。 当反相放大电路不工作时，MOS开关打开。

公开(公告)号：US06169771A

公开(公告)日：2001-01-02

申请号：US09014264

申请日：1998-01-27

申请人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Xiaoling Oin ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

发明人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Xiaoling Oin ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

IPC分类号： H04L2706

CPC分类号： H03H17/0254 ,  H04B1/7093

摘要： In one aspect, the present invention provides a low power consumption matched filter. The signal received at an input terminal is input to a shift register having stages equal to the spread code length number after conversion into digital signals in an A/D converter. The outputs of the shift register stages are input to XOR circuits set corresponding to each stage, so that XOR operations are performed between the outputs and corresponding spread code bits d1 to dN. The outputs of the XOR circuits are analogously added in an analog adder and output from an output terminal. In another aspect, a filter circuit uses an analog operation circuit to prevent lowered operational accuracy caused by residual charge. Input analog signals successively undergo sampling and holding in sample-and-hold circuits, are multiplied by coefficients stored in a shift register by multiplication circuits, and added in an addition circuit. Sample data transmission error storage is prevented by shifting coefficients in the shift register. Sample-and-hold circuits and multiplication circuits are formed by analog operation circuits, and each include a switch for canceling the residual charge. The sample-and-hold circuits and multiplication circuits normally working are refreshed sequentially by providing circuits for replacing their function. The addition circuit is refreshed in the same way.

摘要翻译： 一方面，本发明提供一种低功耗匹配滤波器。 在A / D转换器转换成数字信号之后，在输入端接收的信号被输入到具有等于扩展码长度数的级的移位寄存器。 移位寄存器级的输出被输入到对应于每一级的XOR电路，从而在输出和对应的扩展码位d1至dN之间执行异或运算。 XOR电路的输出类似地添加到模拟加法器中并从输出端子输出。 另一方面，滤波器电路使用模拟运算电路来防止由剩余电荷引起的运算精度降低。 输入模拟信号在采样保持电路中连续进行采样和保持，乘以乘法电路存储在移位寄存器中的系数，并加入加法电路。 通过移位寄存器中的系数来防止采样数据传输错误存储。 采样保持电路和乘法电路由模拟操作电路形成，并且每个都包括用于消除剩余电荷的开关。 正常工作的采样保持电路和乘法电路通过提供更换其功能的电路依次刷新。 加法电路以相同的方式刷新。

公开(公告)号：US06031415A

公开(公告)日：2000-02-29

申请号：US733820

申请日：1996-10-18

申请人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Mamoru Sawahashi ,  Fumiyuki Adachi ,  Sunao Takatori

发明人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Mamoru Sawahashi ,  Fumiyuki Adachi ,  Sunao Takatori

IPC分类号： H04J13/00 ,  H03H17/02 ,  H04B1/7093 ,  H03K5/00 ,  H03D1/00

CPC分类号： H03H17/0254 ,  H04B1/707

摘要： The present invention provides a matched filter circuit available for processing long P/N codes in a small size circuit. A matched filter circuit according to the present invention performs the following processes in the proposed invention: i) sampling and holding circuits multiply part of the number of a long code; ii) multipliers are input in parallel to the sampling and holding circuit from the first multiplier register which can hold as many PN codes as the number of the sampling and holding circuits in i); iii) the PN codes are stored in the second multiplier register of the same capacity of the first multiplier resister when there is a PN code to be used sequentially to be PN codes; and iv) the PN codes in the second multiplier register are transmitted in parallel to the first multiplier register. The PN code is input to the second multiplier register in serial.

摘要翻译： 本发明提供了可用于处理小尺寸电路中的长P / N码的匹配滤波器电路。 根据本发明的匹配滤波器电路在所提出的发明中执行以下处理：i）采样和保持电路乘以长码的数量的一部分; ii）乘法器与来自第一乘法器寄存器的采样和保持电路并联输入，其可以容纳与i）中的采样和保持电路的数量一样多的PN码; iii）当存在要被顺序使用的PN码为PN码时，PN码存储在第一乘法器电阻相同容量的第二乘法器寄存器中; 和iv）第二乘法器寄存器中的PN码并行发送到第一乘法器寄存器。 PN码以串行方式输入到第二个乘法器寄存器。

公开(公告)号：US5926512A

公开(公告)日：1999-07-20

申请号：US735787

申请日：1996-10-23

申请人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

发明人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

IPC分类号： H04J13/00 ,  H03H11/04 ,  H03H17/02 ,  H03H19/00 ,  H04B1/7093 ,  H03D1/00 ,  H04L27/06

CPC分类号： H03H11/04 ,  H03H17/0254 ,  Y02B60/50

摘要： A matched filter circuit for mobile communications is disclosed. The circuit may be fabricated in a small size using large-scale integration and can perform high-speed processing and double sampling at a reduced rate of power consumption. In one embodiment, a plurality of sampling and holding circuits each including a switch are divided into two groups. A control circuit successively closes one of the switches in the first group every chip time, while successively closing one of the switches in the second group at a timing shifted by one-half chip time from that of the first group, thereby enabling a double-sampling operation. Outputs of the sampling and holding circuits in each group are summed by an analog circuit with a high degree of linearity, resulting in a high processing speed combined with a reduced circuit size and power consumption.

摘要翻译： 公开了一种用于移动通信的匹配滤波器电路。 该电路可以使用大规模集成在小尺寸上制造，并且可以以降低的功率消耗来执行高速处理和双重采样。 在一个实施例中，每个包括开关的多个采样和保持电路被分成两组。 控制电路在每个码片时间连续地闭合第一组中的一个开关，同时以与第一组相比半个码片时间偏移的时间顺序地关闭第二组中的一个开关，由此， 抽样操作。 每个组中的采样和保持电路的输出由具有高线性度的模拟电路相加，导致高处理速度以及减小的电路尺寸和功耗。

公开(公告)号：US5910948A

公开(公告)日：1999-06-08

申请号：US955613

申请日：1997-10-22

申请人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

发明人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Mamoru Sawahashi ,  Fumiyuki Adachi

IPC分类号： H04B1/707 ,  H04B1/708 ,  H04B1/7083 ,  H04B7/26 ,  H04J13/00 ,  H04L7/00 ,  H04W36/00 ,  H04W48/18 ,  H04W56/00 ,  H04B7/216

CPC分类号： H04W48/18 ,  H04B1/70735 ,  H04B1/70775 ,  H04B1/708 ,  H04B1/7083 ,  H04B1/7093 ,  H04B1/7117 ,  H04B2201/70702 ,  H04W36/00

摘要： The present invention realizes a rapid and efficient cell search and small-size instrument for an asynchronous DS-CDMA cellular system. This cell search detects the correlation between the received signal and the short code of the control channel, and matched filter 22 detects the maximum electric power correlation peak location. Next, using correlators 28-1 to 28-n which are parallelly set in a plurality for RAKE processing with plurality, identifies the long code that is set in the system with the detected long code timing. After the long code is synchronized, a multipath signal is received using 28-1 to 28-n, and the data is judged by RAKE processing. When peripheral cell search is executed, after long code timing is detected by using matched filter 22, the long code of the candidate peripheral cell is designated using the same matched filter. Handover is safely realized by receiving the signal from the connected base station by correlators 28-1 to 28-n, and the base station signal through handover by 22.

摘要翻译： 本发明实现了用于异步DS-CDMA蜂窝系统的快速且有效的小区搜索和小尺寸仪器。 该小区搜索检测接收信号与控制信道的短码之间的相关性，匹配滤波器22检测最大功率相关峰位置。 接下来，使用多个并行设置为用于RAKE处理的多个的相关器28-1至28-n识别具有检测到的长码定时的系统中设置的长码。 在长代码同步之后，使用28-1至28-n接收多路径信号，并且通过RAKE处理来判断数据。 当执行外围小区搜索时，在通过使用匹配滤波器22检测长码定时之后，使用相同的匹配滤波器来指定候选周边小区的长码。 通过由相关器28-1至28-n接收来自所连接的基站的信号，以及通过22次切换的基站信号来安全地实现切换。