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47 条记录 (耗时 0.025 秒)

    Spread spectrum communications system for high-speed communications
    1.
    发明授权
    Spread spectrum communications system for high-speed communications 失效
    扩频通信系统，用于高速通信

    公开(公告)号：US5930290A

    公开(公告)日：1999-07-27

    申请号：US841217

    申请日：1997-04-30

    申请人： Changming Zhou ,  Guoliang Shou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Kenzo Urabe

    发明人： Changming Zhou ,  Guoliang Shou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori ,  Kenzo Urabe

    IPC分类号： H04B1/707 ,  H04B1/7093 ,  H04J13/10 ,  H04B15/00 ,  H04B7/216

    CPC分类号： H04J13/0077 ,  H04B1/7093

    摘要： A fast spread spectrum communication system is provided, having fewer circuits and requiring fewer PN codes to be assigned to a user. A series of digital data to be transmitted, is divided into 4-bit frames. The 4-bit data of each frame is divided into the first through fourth elements in a predetermined order. The first complex number is constructed by the first and second elements, and the second complex number is determined according to the value of the third and fourth elements. The spectrum of the data to be transmitted is spread by multiplying these complex numbers. Four matched filters despread a received signal by different combinations of PN codes stored in a receiver. The first through fourth elements are recovered according to the outputs of the matched filters.

    摘要翻译： 提供了一种快速扩频通信系统，具有较少的电路并且需要较少的PN码来分配给用户。 要发送的一系列数字数据被分为4位帧。 每帧的4位数据按预定顺序分成第一至第四元素。 第一复数由第一和第二元素构成，第二复数根据第三和第四元素的值确定。 要传输的数据的频谱通过乘以这些复数来传播。 四个匹配滤波器通过存储在接收机中的PN码的不同组合对接收信号进行解扩。 根据匹配滤波器的输出，恢复第一至第四元件。

    Matched filter system
    2.
    发明授权
    Matched filter system 失效
    匹配过滤系统

    公开(公告)号：US5844937A

    公开(公告)日：1998-12-01

    申请号：US744954

    申请日：1996-11-07

    申请人： Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Kenzo Urabe ,  Sunao Takatori

    发明人： Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Kenzo Urabe ,  Sunao Takatori

    IPC分类号： H03H15/00 ,  H03H11/04 ,  H03H17/02 ,  H04B1/7093 ,  H04J13/00 ,  H04B15/00

    CPC分类号： H04B1/7093 ,  H03H11/04 ,  H03H17/0254

    摘要： The present invention solves the conventional problems and has an object to provide a matched filter system of high process in speed, a small size and low electric power consumption. The matched filter circuits of each matched filter set is allocated different n combinations of M/n digits selected from the M length PN code sequence picking one out of every n digits, cyclically performs sampling every 1 chip time duration the input signals to be inputted to each set constructed by matched filter circuits by n sets each of which including n matched filter circuits, and calculates the sum of outputs of all matched filter circuits.

    摘要翻译： 本发明解决了以往的问题，其目的在于提供一种速度快，体积小，功耗低的匹配滤波系统。 每个匹配滤波器组的匹配滤波器电路被分配从从n个数字中选出一个的M个长度PN码序列中选择的M / n个数字的不同n个组合，每1个码片持续时间周期地执行要输入的输入信号的采样 每组由匹配滤波器电路构成，每组包括n个匹配滤波器电路，并且计算所有匹配滤波器电路的输出之和。

    Demodulator for CDMA spread spectrum communication using multiple pn codes
    3.
    发明授权
    Demodulator for CDMA spread spectrum communication using multiple pn codes 失效
    用于使用多个pn码的CDMA扩频通信的解调器

    公开(公告)号：US5812546A

    公开(公告)日：1998-09-22

    申请号：US802635

    申请日：1997-02-19

    申请人： Changming Zhou ,  Guoliang Shou ,  Xuping Zhou ,  Makoto Yamamoto ,  Kenzo Urabe ,  Sunao Takatori

    发明人： Changming Zhou ,  Guoliang Shou ,  Xuping Zhou ,  Makoto Yamamoto ,  Kenzo Urabe ,  Sunao Takatori

    IPC分类号： H04B1/707 ,  H04B1/7093 ,  H04J13/04

    CPC分类号： H04B1/7093

    摘要： The demodulator has a plurality of matched filters in parallel. Each matched filter has a different binary PN code, a plurality of sample holders, a plurality of multipliers, an adder, and a controller. The sample holders has a common input, a switch, a first capacitor, a first inverse amplifier with an output and an input connected to the common input through the switch and the capacitor, and a first feedback capacitor for feeding the output of the first inverse amplifier back to the input. Each multiplier has a first and second sub-multiplexers, one of sub-multiplexer selecting corresponding sample holder output and another sub-multiplexer selecting a reference voltage.

    摘要翻译： 解调器具有并联的多个匹配滤波器。 每个匹配滤波器具有不同的二进制PN码，多个采样保持器，多个乘法器，加法器和控制器。 样本保持器具有公共输入，开关，第一电容器，具有输出的第一反相放大器和通过开关和电容器连接到公共输入的输入端，以及用于馈送第一反相器的输出的第一反馈电容器 放大器返回输入。 每个乘法器具有第一和第二子复用器，其中一个子复用器选择对应的采样保持器输出，另一个副多路复用器选择参考电压。

    Receiver for code division multiple access communication system
    4.
    发明授权
    Receiver for code division multiple access communication system 失效
    接收机用于码分多址通信系统

    公开(公告)号：US5974038A

    公开(公告)日：1999-10-26

    申请号：US864784

    申请日：1997-05-29

    申请人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori

    发明人： Guoliang Shou ,  Changming Zhou ,  Xuping Zhou ,  Makoto Yamamoto ,  Sunao Takatori

    IPC分类号： H04B1/707 ,  H04B1/7075 ,  H04B1/7093 ,  H04B1/7115 ,  H04L7/00 ,  H04B7/216

    CPC分类号： H04B1/708 ,  H04B1/7093 ,  H04B1/7115 ,  H04B2201/70709

    摘要： This invention reduces electric power consumption of a CDMA communication system receiver while it is in the wait mode. A received spread spectrum signal is demodulated in multiplication means into baseband signals Ri and Rq, and inputted into a complex matched filter. This filter is intermittently driven by supply voltage control means to perform acquisition of received signals. When an electric power calculation circuit detects the output of the filter to reach a peak equal to or greater than a predetermined value, the received signals undergo acquisition by controlling n number of correlators 26-1 to 26-n to work by a correlator controlling circuit. Moreover, de-spreading is performed. The outputs from each correlator 46-1 to 26-n are given to a RAKE combiner and demodulated by the RAKE by a combining and demodulating circuit.

    摘要翻译： 本发明在CDMA通信系统接收机处于等待模式时降低电力消耗。 接收的扩频信号在乘法装置中被解调为基带信号Ri和Rq，并输入到复匹配滤波器中。 该滤波器由电源电压控制装置间歇地驱动，以执行接收信号的采集。 当电力计算电路检测到滤波器的输出达到等于或大于预定值的峰值时，通过控制n个相关器26-1至26-n来由相关器控制电路工作来接收接收的信号 。 此外，进行解扩。 来自每个相关器46-1至26-n的输出被提供给RAKE组合器，并由RAKE通过组合和解调电路进行解调。

    Matched filter circuit
    5.
    发明授权
    Matched filter circuit 失效
    匹配滤波电路

    公开(公告)号：US5872466A

    公开(公告)日：1999-02-16

    申请号：US686950

    申请日：1996-07-26

    申请人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori

    发明人： Guoliang Shou ,  Changming Zhou ,  Makoto Yamamoto ,  Sunao Takatori

    IPC分类号： H03H11/04 ,  H03H17/02 ,  H04B1/707 ,  H04B1/7093 ,  H04L7/00 ,  H04L7/10 ,  H03K5/00

    CPC分类号： H03H11/04 ,  H03H17/0254

    摘要： A matched filter with reduced electric power consumption is disclosed. The matched filter circuit power consumption is reduced by stopping the electric power supply to an unnecessary circuit since input signal is partially sampled just after an acquisition. Since the spreading code is 1 bit data string, the input signal sampled and held is branched out into the signal groups "1" and "-1" by a multiplexer. The signals in each groups are added in parallel by a capacitive coupling, and the electric power is supplied in the circuit intermittently.

    摘要翻译： 公开了具有降低的电力消耗的匹配滤波器。 由于输入信号在采集之后被部分采样，因此通过停止对不必要的电路的电力来降低匹配滤波器电路的功耗。 由于扩展码是1位数据串，采样和保持的输入信号通过多路复用器分支到信号组“1”和“-1”。 各组中的信号通过电容耦合并联并且在电路中间歇地供电。

    Inverted amplifying circuit
    6.
    发明授权
    Inverted amplifying circuit 失效
    反相放大电路

    公开(公告)号：US5783961A

    公开(公告)日：1998-07-21

    申请号：US764637

    申请日：1996-12-11

    申请人： Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Sunao Takatori

    发明人： Changming Zhou ,  Guoliang Shou ,  Makoto Yamamoto ,  Sunao Takatori

    IPC分类号： H03K19/0948 ,  H03F1/02 ,  H03F1/34 ,  H03F3/46 ,  H03F3/72 ,  H03K5/153 ,  H03H11/26

    CPC分类号： H03F3/72

    摘要： The present invention has an object to provide an inverted amplifying circuit with improved accuracy of output and reduced electric power consumption. In an inverted amplifying circuit according to the present invention, a MOS switch is connected between pMOS and nMOS of a CMOS inverter and between balancing resistances. The MOS switch is opened when the inverted amplifying circuit does not work.

    摘要翻译： 本发明的目的是提供一种具有提高的输出精度和降低的电力消耗的反相放大电路。 在根据本发明的反相放大电路中，MOS开关连接在CMOS反相器的pMOS和nMOS之间以及平衡电阻之间。 当反相放大电路不工作时，MOS开关打开。

    Vector absolute--value calculation circuit
    7.
    发明授权
    Vector absolute--value calculation circuit 失效
    矢量绝对值计算电路

    公开(公告)号：US5958002A

    公开(公告)日：1999-09-28

    申请号：US905784

    申请日：1997-08-12

    申请人： Changming Zhou ,  Guoliang Shou ,  Kunihiko Suzuki ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

    发明人： Changming Zhou ,  Guoliang Shou ,  Kunihiko Suzuki ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

    IPC分类号： G06G7/25 ,  G06G7/22 ,  G06G7/00 ,  G06G7/16

    CPC分类号： G06G7/22

    摘要： A highly accurate vector absolute-value calculation circuit uses analog processing and minimal hardware. Signal voltages corresponding to an I component (real number part) and a Q component (imaginary number part) are input to a first absolute-value calculation circuit 13 and a second absolute-value calculation circuit 14 through terminals 11 and 12, respectively, and they are each converted into absolute-value signals. The component I absolute-value and component Q absolute-value are compared in a comparison circuit 20. According to the result, the larger absolute-value signals are output to an input capacitor 23 of a neural computation circuit, and the smaller absolute-value signals are output to an input capacitor 24 by controlling multiplexers 21 and 22. The capacity ratio of a feedback capacitor 26 of a neural computation circuit and input capacitors 23 and 24 is 11:10:5. The complex number absolute-value calculated by the following formula is output from an output terminal 27. ##EQU1##

    摘要翻译： 高精度矢量绝对值计算电路采用模拟处理和最小硬件。 对应于I分量（实数部分）和Q分量（虚数部分）的信号电压分别通过端子11和12输入到第一绝对值计算电路13和第二绝对值计算电路14，以及 它们都被转换为绝对值信号。 在比较电路20中比较分量I绝对值和分量Q绝对值。根据结果，较大的绝对值信号被输出到神经计算电路的输入电容器23，并且较小的绝对值 通过控制多路复用器21和22将信号输出到输入电容器24.神经计算电路和输入电容器23和24的反馈电容器26的容量比为11:10:5。 从输出端子27输出由下式计算的复数绝对值。

    Weight addition circuit
    9.
    发明授权
    Weight addition circuit 失效
    加权电路

    公开(公告)号：US5815021A

    公开(公告)日：1998-09-29

    申请号：US686761

    申请日：1996-07-26

    申请人： Guoliang Shou ,  Changming Zhou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

    发明人： Guoliang Shou ,  Changming Zhou ,  Kazunori Motohashi ,  Makoto Yamamoto ,  Sunao Takatori

    IPC分类号： G06G7/14 ,  G06J1/00 ,  G06G7/16

    CPC分类号： G06J1/00 ,  G06G7/14

    摘要： The present invention provides a weighted addition circuit for sampling, holding and performing weighted addition by a circuit smaller than a conventional one. In the weighted addition circuit of to the present invention, a capacitive coupling is connected to a plurality of switches which are further connected only to an input voltage. A voltage is held and a weight is added in the capacitive coupling.

    摘要翻译： 本发明提供一种加权加法电路，用于通过比传统电路小的电路进行采样，保持和执行加权相加。 在本发明的加权加法电路中，电容耦合连接到多个开关，该开关进一步仅与输入电压相连。 在电容耦合中保持电压并加上重量。