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    METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING
    43.
    发明申请
    METHOD AND STRUCTURE TO PROCESS THICK AND THIN FINS AND VARIABLE FIN TO FIN SPACING 审中-公开

    公开(公告)号：US20070284669A1

    公开(公告)日：2007-12-13

    申请号：US11838934

    申请日：2007-08-15

    申请人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

    发明人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

    IPC分类号： H01L29/76

    CPC分类号： B07C5/344 ,  G01R31/2831

    摘要： Disclosed is an integrated circuit with multiple semiconductor fins having different widths and variable spacing on the same substrate. The method of forming the circuit incorporates a sidewall image transfer process using different types of mandrels. Fin thickness and fin-to-fin spacing are controlled by an oxidation process used to form oxide sidewalls on the mandrels, and more particularly, by the processing time and the use of intrinsic, oxidation-enhancing and/or oxidation-inhibiting mandrels. Fin thickness is also controlled by using sidewalls spacers combined with or instead of the oxide sidewalls. Specifically, images of the oxide sidewalls alone, images of sidewall spacers alone, and/or combined images of sidewall spacers and oxide sidewalls are transferred into a semiconductor layer to form the fins. The fins with different thicknesses and variable spacing can be used to form a single multiple-fin FET or, alternatively, various single-fin and/or multiple-fin FETs.

    Virtual array failover
    44.
    发明申请
    Virtual array failover 有权
    虚拟阵列故障切换

    公开(公告)号：US20070283186A1

    公开(公告)日：2007-12-06

    申请号：US11318675

    申请日：2005-12-27

    申请人： Kiran Madnani ,  Adi Ofer ,  Jeffrey Brown

    发明人： Kiran Madnani ,  Adi Ofer ,  Jeffrey Brown

    IPC分类号： G06F11/16 ,  G06F12/08

    CPC分类号： G06F11/2094 ,  G06F3/0617 ,  G06F3/0647 ,  G06F3/067 ,  G06F11/1662 ,  G06F11/2082 ,  G06F11/2097

    摘要： Failover is provided between groups of logical units of storage presented as virtual arrays. A primary virtual array has at least one primary virtual port coupled to a fabric, each primary virtual port having a source virtual port name and a source virtual port address. A secondary virtual array has one or more secondary virtual ports coupled to the fabric, each secondary virtual port having a secondary virtual port name and a secondary virtual port address. All data resident on the primary virtual array is copied to the secondary virtual array. If a failure occurs in the primary virtual array, the secondary virtual port names and LUN names and numbers are replaced with the primary virtual port names and LUN names and numbers. The fabric then updates its name server database so that the database associates the primary virtual port names and LUN names and numbers with the secondary virtual port addresses.

    摘要翻译： 在作为虚拟阵列呈现的逻辑存储单元组之间提供故障转移。 主虚拟阵列具有耦合到结构的至少一个主虚拟端口，每个主虚拟端口具有源虚拟端口名称和源虚拟端口地址。 辅助虚拟阵列具有耦合到该结构的一个或多个辅助虚拟端口，每个辅助虚拟端口具有辅助虚拟端口名称和次要虚拟端口地址。 驻留在主虚拟阵列上的所有数据都将复制到辅助虚拟阵列。 如果主虚拟阵列中发生故障，则辅助虚拟端口名称和LUN名称和数字将替换为主虚拟端口名称和LUN名称和数字。 然后织物更新其名称服务器数据库，以便数据库将主虚拟端口名称和LUN名称和数字与辅助虚拟端口地址相关联。

    Method and apparatus for detecting and viewing similar programs within a video system
    45.
    发明申请
    Method and apparatus for detecting and viewing similar programs within a video system 审中-公开
    用于在视频系统内检测和查看类似节目的方法和装置

    公开(公告)号：US20070261070A1

    公开(公告)日：2007-11-08

    申请号：US11827233

    申请日：2007-07-11

    申请人： Jeffrey Brown ,  Philip Hsiao ,  Craig Finseth

    发明人： Jeffrey Brown ,  Philip Hsiao ,  Craig Finseth

    IPC分类号： H04N7/16

    CPC分类号： H04N7/162 ,  G06F3/0482 ,  H04N7/163 ,  H04N21/4331 ,  H04N21/4348 ,  H04N21/44222 ,  H04N21/466 ,  H04N21/4663 ,  H04N21/4668 ,  H04N21/4826 ,  H04N21/812 ,  H04N21/84

    摘要： A device that detects and displays similar programs within a video system includes a memory, a display and a receiver that receives an input stream of television program content and electronic program guide data, wherein the program guide data includes a plurality of attributes characterizing television programs within the television program content. The receiver separates electronic program guide data from the input stream while the memory stores the electronic program guide data separated from the input stream. Upon receiving a first user request, a controller compares a first set of attributes relating to at least one television program within the television content with second sets of attributes relating to further television programs within the television program content to determine a correlation between the first television program and each of the further television programs. In this manner, the controller identifies the television programs that have attributes that are similar to the attributes of the first television program based on the correlation and displays indications of the television programs found to be similar.

    摘要翻译： 一种在视频系统内检测和显示类似节目的设备包括存储器，显示器和接收器，其接收电视节目内容和电子节目指南数据的输入流，其中节目指南数据包括表征电视节目内部的电视节目的多个属性 电视节目内容。 接收器将电子节目指南数据与输入流分开，而存储器存储与输入流分离的电子节目指南数据。 在接收到第一用户请求后，控制器将与电视内容中的至少一个电视节目相关的第一组属性与电视节目内容中的其他电视节目相关的第二组属性进行比较，以确定第一电视节目 和每个进一步的电视节目。 以这种方式，控制器基于相关性来识别具有与第一电视节目的属性类似的属性的电视节目，并且显示被发现相似的电视节目的指示。

    Methods and apparatus for reducing command reissue latency
    46.
    发明申请
    Methods and apparatus for reducing command reissue latency 审中-公开
    减少命令重发延迟的方法和装置

    公开(公告)号：US20070174556A1

    公开(公告)日：2007-07-26

    申请号：US11340751

    申请日：2006-01-26

    申请人： Jeffrey Brown ,  Michael Carnevale ,  Charles Johns ,  David Krolak ,  Thuong Truong

    发明人： Jeffrey Brown ,  Michael Carnevale ,  Charles Johns ,  David Krolak ,  Thuong Truong

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0831

    摘要： In a first aspect, a first method of reducing reissue latency of a command received in a command processing pipeline from one of a plurality of units coupled to a bus is provided. The first method includes the steps of (1) from a first unit coupled to the bus, receiving a first command on the bus requiring access to a cacheline; (2) determining a state of the cacheline required by the first command by accessing cacheline state information stored in each of the plurality of units; (3) determining whether a second command received on the bus requires access to the cacheline before the state of the cacheline is returned to the first unit; and (4) if so, storing the second command in a buffer. Numerous other aspects are provided.

    摘要翻译： 在第一方面，提供了一种减少在命令处理流水线中从耦合到总线的多个单元之一接收的命令的重发等待时间的第一方法。 第一种方法包括以下步骤：（1）从耦合到总线的第一单元接收需要访问高速缓存线的总线上的第一命令; （2）通过访问存储在所述多个单元中的每个单元中的高速缓存行状态信息来确定所述第一命令所需的高速缓存行的状态; （3）在高速缓存行的状态返回到第一单元之前，确定在总线上接收的第二命令是否需要访问高速缓存线; 和（4）如果是，则将第二命令存储在缓冲器中。 提供了许多其他方面。

    Storage processor architecture for high throughput applications providing efficient user data channel loading
    48.
    发明授权
    Storage processor architecture for high throughput applications providing efficient user data channel loading 有权
    高吞吐量应用的存储处​​理器架构，提供高效的用户数据通道加载

    公开(公告)号：US07209979B2

    公开(公告)日：2007-04-24

    申请号：US10113027

    申请日：2002-03-29

    申请人： Robert Solomon ,  Jeffrey Brown

    发明人： Robert Solomon ,  Jeffrey Brown

    IPC分类号： G06F15/16

    CPC分类号： G06F3/0613 ,  G06F3/0655 ,  G06F3/0689 ,  G06F11/1008 ,  G06F11/2089

    摘要： A storage processor particularly suited to RAID systems provides high throughput for applications such as streaming video data. An embodiment is configured as an ASIC with a high degree of parallelism in its interconnections. The communications architecture provides saturation of user data pathways with low complexity and low latency by employing multiple memory channels under software control, an efficient parity calculation mechanism and other features.

    摘要翻译： 特别适用于RAID系统的存储处理器为诸如流视频数据的应用提供高吞吐量。 实施例被配置为在其互连中具有高度并行性的ASIC。 通信架构通过在软件控制下采用多个存储器通道，高效的奇偶校验计算机制和其他特性，提供低复杂度和低延迟的用户数据路径饱和。

    E-Fuse and anti-E-Fuse device structures and methods
    49.
    发明申请
    E-Fuse and anti-E-Fuse device structures and methods 审中-公开
    电子熔断器和反电子保险丝器件的结构和方法

    公开(公告)号：US20060220174A1

    公开(公告)日：2006-10-05

    申请号：US11440199

    申请日：2006-05-24

    申请人： Jeffrey Brown ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

    发明人： Jeffrey Brown ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Standard photolithography is used to pattern and fabricate a final polysilicon wafer imaged structure which is smaller than normal allowable photo-lithographic minimum dimensions. Three different methods are provided to produce such sub-minimum dimension structures, a first method uses a photolithographic mask with a sub-minimum space between minimum size pattern features of the mask, a second method uses a photolithographic mask with a sub-minimum widthwise jog or offset between minimum size pattern features of the mask, and a third method is a combination of the first and second methods. Each of the three methods can be used with three different embodiments, a first embodiment is a polysilicon E-Fuse with a sub-minimum width polysilicon fuse line, a second embodiment is a work function altered/programmed self-aligned MOSFET E-Fuse with a sub-minimum width fuse line, and a third embodiment is a polysilicon MOSFET E-Fuse with a sub-minimum width fuse line which is programmed with a low trigger voltage snapback.

    摘要翻译： 使用标准光刻法来图案化和制造最终的多晶硅晶片成像结构，该结构小于正常允许光刻最小尺寸。 提供了三种不同的方法来产生这样的次最小维度结构，第一种方法使用具有掩模的最小尺寸图案特征之间的亚最小空间的光刻掩模，第二种方法使用光刻掩模与次最小宽度方向点动 或掩模的最小尺寸图案特征之间的偏移，第三种方法是第一和第二方法的组合。 三种方法中的每一种可以与三种不同的实施例一起使用，第一实施例是具有亚最小宽度多晶硅熔丝线的多晶硅E熔丝，第二实施例是工作功能改变/编程的自对准MOSFET E-Fuse，具有 亚最小宽度熔丝线，第三实施例是具有低电平触发电压快速编程的亚最小宽度熔丝线的多晶硅MOSFET E-Fuse。