公开(公告)号：US20060172469A1

公开(公告)日：2006-08-03

申请号：US11312473

申请日：2005-12-21

Applicant: Jia-Xing Lin ,  Yu-Cheng Chen ,  Chi-Lin Chen

Inventor： Jia-Xing Lin ,  Yu-Cheng Chen ,  Chi-Lin Chen

IPC: H01L21/84 ,  H01L21/20

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/2026 ,  H01L27/1296 ,  H01L29/66757 ,  H01L29/78675

Abstract: An amorphous silicon (a-Si) layer is first formed on a substrate, and the a-Si layer is next patterned to form silicon islands for defining device active regions. Then, a single shot laser beam with long pulse is utilized to irradiate each silicon island, and lateral growth crystallization is induced in each silicon island for transforming a-Si into polycrystalline silicon (poly-Si). Finally, the general subsequent processes for thin film transistor (TFT) fabrication are performed in turn to fabricate poly-Si TFTs.

Abstract translation: 首先在衬底上形成非晶硅（a-Si）层，然后将a-Si层图案化以形成用于限定器件有源区的硅岛。 然后，利用具有长脉冲的单次激光束照射每个硅岛，并且在每个硅岛中诱导横向生长结晶以将a-Si转化为多晶硅（poly-Si）。 最后，依次进行薄膜晶体管（TFT）制造的一般后续处理以制造多晶硅TFT。

公开(公告)号：US07060541B2

公开(公告)日：2006-06-13

申请号：US10673325

申请日：2003-09-30

Applicant: Chi-Shen Lee ,  Cheng-Chung Chen ,  Chi-Lin Chen ,  Chai-Yuan Sheu

Inventor： Chi-Shen Lee ,  Cheng-Chung Chen ,  Chi-Lin Chen ,  Chai-Yuan Sheu

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L27/124 ,  H01L27/1255

Abstract: A method of fabricating a thin film transistor (TFT) array involves ion replacement by oxidation-reduction processes for implementing the metal wiring layout of TFT-LCDs. This can overcome metal etching difficulties and achieve automatic alignment. The method of the invention replaces traditional lithographic etching techniciues.

Abstract translation: 制造薄膜晶体管（TFT）阵列的方法涉及通过用于实现TFT-LCD的金属布线布局的氧化还原处理的离子替换。 这可以克服金属蚀刻困难，实现自动对准。 本发明的方法取代了传统的光刻蚀刻技术。

公开(公告)号：US20060088986A1

公开(公告)日：2006-04-27

申请号：US11222804

申请日：2005-09-12

Applicant: Jia-Xing Lin ,  Chi-Lin Chen ,  Yu-Cheng Chen ,  Po-Hao Tsai

Inventor： Jia-Xing Lin ,  Chi-Lin Chen ,  Yu-Cheng Chen ,  Po-Hao Tsai

IPC: H01L21/20

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2026 ,  H01L27/1281 ,  H01L29/66757

Abstract: An amorphous silicon layer and at least a heat-retaining layer are formed on a substrate in turn. Wherein, the heat-retaining layer is controlled to have an anti-reflective thickness for reducing the threshold laser energy to effect the melting of the amorphous silicon layer. Then, a laser irradiation process is performed to transform the amorphous silicon layer into a polycrystalline silicon layer. During the laser irratiation process, a portion of the laser energy transmits the heat-retaining layer to effect the melting of the amorphous silicon layer, and another portion of the laser energy is absorbed by the heat-retaining layer.

Abstract translation: 依次在基板上形成非晶硅层和至少一个保温层。 其中，保温层被控制为具有用于降低阈值激光能量以实现非晶硅层熔化的抗反射厚度。 然后，执行激光照射处理以将非晶硅层转变成多晶硅层。 在激光照射过程中，激光能量的一部分透过保温层来实现非晶硅层的熔化，另一部分激光能被保温层吸收。

公开(公告)号：US20060043072A1

公开(公告)日：2006-03-02

申请号：US11194314

申请日：2005-08-01

Applicant: Yu-Cheng Chen ,  Jia-Xing Lin ,  Chi-Lin Chen

Inventor： Yu-Cheng Chen ,  Jia-Xing Lin ,  Chi-Lin Chen

IPC: C03C15/00

CPC classification number: H01L21/02675 ,  C03C15/00 ,  C03C15/02 ,  C03C23/0025 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2026 ,  H01L21/32115 ,  H01L29/6675 ,  H01L29/78606

Abstract: A method for planarizing polysilicon comprises providing a substrate, forming a dielectric layer on the substrate, forming an amorphous silicon film on the dielectric layer, etching the amorphous silicon film to remove native oxide formed on a surface of the amorphous silicon film, exposing the surface of the amorphous silicon film to a first radiation source to polycrystallize the amorphous silicon film into a polysilicon film, etching the polysilicon film to remove weak bonded silicon formed on a surface of the polysilicon film, and exposing the surface of the polysilicon film to a second radiation source to reflow the polysilicon film.

Abstract translation: 一种用于平坦化多晶硅的方法包括：提供衬底，在衬底上形成电介质层，在电介质层上形成非晶硅膜，蚀刻非晶硅膜以去除在非晶硅膜的表面上形成的自然氧化物， 将所述非晶硅膜施加到第一辐射源以将所述非晶硅膜多晶化为多晶硅膜，蚀刻所述多晶硅膜以去除在所述多晶硅膜的表面上形成的弱键合硅，并将所述多晶硅膜的表面暴露于第二 辐射源来回流多晶硅膜。

公开(公告)号：US20050136612A1

公开(公告)日：2005-06-23

申请号：US10780589

申请日：2004-02-19

Applicant: Jia-Xing Lin ,  Chi-Lin Chen ,  Yu-Cheng Chen

Inventor： Jia-Xing Lin ,  Chi-Lin Chen ,  Yu-Cheng Chen

IPC: H01L21/20 ,  H01L21/268 ,  H01L21/336 ,  H01L29/786 ,  H01L21/76

CPC classification number: H01L21/02686 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/2026 ,  H01L21/268 ,  H01L27/1296 ,  H01L29/66757 ,  H01L29/78675

Abstract: An amorphous silicon layer is formed on a substrate, and then a protective layer and a reflective layer are formed in turn to form a film stack on portions of the amorphous silicon layer. The reflective layer is a metal material with reflectivity of laser, and the protective layer is able to prevent metal diffusion. When an excimer laser heats the amorphous silicon layer to crystallize the amorphous silicon, nucleation sites are formed in the amorphous silicon layer under the film stack of the protective layer and the reflective layer. Next, laterally expanding crystallization occurs in the amorphous silicon layer to form poly-silicon having crystal grains with size of micrometers and high grain order.

Abstract translation: 在基板上形成非晶硅层，然后依次形成保护层和反射层，以在非晶硅层的部分上形成膜堆叠。 反射层是具有激光反射率的金属材料，保护层能够防止金属扩散。 当准分子激光器加热非晶硅层以使非晶硅结晶时，在保护层和反射层的膜堆叠下面的非晶硅层中形成成核位置。 接下来，在非晶硅层中发生横向膨胀结晶，形成晶粒大小为微米，晶粒度高的多晶硅。

公开(公告)号：US20050073619A1

公开(公告)日：2005-04-07

申请号：US10687759

申请日：2003-10-20

Applicant: Yu-Cheng Chen ,  Chi-Lin Chen

Inventor： Yu-Cheng Chen ,  Chi-Lin Chen

IPC: G09F9/30 ,  G02F1/1362 ,  H01L23/522 ,  H01L27/12 ,  G02F1/136

CPC classification number: H01L27/12 ,  G02F1/136286 ,  H01L23/5221 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A multi-layered complementary wire structure and a manufacturing method thereof are disclosed, comprising a first wire and a second wire. Each of the first and the second wires comprises a main line and a plurality of branch lines located in a different layer from the main line. A plurality contact holes are formed in an insulating layer between the first wire and the second wire to connect the main line of the first wire and the branch lines of the first wire, and connect the main line of the second wire and the branch lines of the second wire. The main line of the first wire is insulated and crossed with the main line of the second wire. The main line of the first wire and the branch lines of the second wire are insulated with each other and located in the same layer. The main line of the second wire and the branch lines of the first wire are insulated with each other and located in the same layer.

Abstract translation: 公开了一种多层互补线结构及其制造方法，包括第一线和第二线。 第一和第二导线中的每一个包括主线和位于与主线不同的层中的多个分支线。 在第一线和第二线之间的绝缘层中形成多个接触孔，以连接第一线的主线和第一线的分支线，并将第二线的主线和 第二根线。 第一根导线的主线绝缘并与第二根导线的主线交叉。 第一线的主线和第二线的分支线彼此绝缘并位于同一层中。 第二线的主线和第一线的分支线彼此绝缘并位于同一层中。

公开(公告)号：US20050048407A1

公开(公告)日：2005-03-03

申请号：US10673326

申请日：2003-09-30

Applicant: Chi-Shen Lee ,  Yung-Fu Wu ,  Chi-Lin Chen ,  Cheng-Chung Chen

Inventor： Chi-Shen Lee ,  Yung-Fu Wu ,  Chi-Lin Chen ,  Cheng-Chung Chen

IPC: G02F1/136 ,  G02F1/1362 ,  G02F1/1368 ,  G03F7/00 ,  H01L21/336 ,  H01L21/77 ,  H01L27/12 ,  H01L27/13 ,  H01L29/786

CPC classification number: G02F1/1368 ,  G02F1/136213 ,  H01L27/1255 ,  H01L27/1288

Abstract: A method of manufacturing a TFT array panel for a LCD disclosers that the gate electrode wiring, transparent conducting electrode, and the first electrode of the storage capacity are formed while the first mask is processing. Then, the selective deposition method is used to process the growth of the first metal wiring. This, therefore, can reduce the numbers of the mask processes. Further, the metal deposition with photo-resist lift-off step is used to implement the layout of the second metal wiring for the consequent transmission lines in the manufacturing process. Finally, the process of the passivation layer deposition is used to implement associated circuits of a TFT array panel for a LCD. The TFT array panel for a LCD for manufacturing circuits can simplify the manufacturing process and reduce the cost.

Abstract translation: 制造LCD阵列面板的方法公开了在第一掩模处理期间形成栅电极布线，透明导电电极和存储容量的第一电极。 然后，选择性沉积法用于处理第一金属布线的生长。 因此，这可以减少掩模处理的数量。 此外，利用光刻胶剥离工序进行金属蒸镀，以在制造工序中实现用于后续传输线的第二金属布线的布局。 最后，钝化层沉积的过程用于实现用于LCD的TFT阵列面板的相关电路。 用于制造电路的LCD的TFT阵列面板可以简化制造工艺并降低成本。

公开(公告)号：US08981209B2

公开(公告)日：2015-03-17

申请号：US13478345

申请日：2012-05-23

Applicant: I-Min Chan ,  Chi-Lin Chen

Inventor： I-Min Chan ,  Chi-Lin Chen

IPC: H01L31/05 ,  H01L31/02 ,  H01L31/0465

CPC classification number: H01L31/02013 ,  H01L31/0201 ,  H01L31/0465 ,  H01L31/05 ,  Y02E10/50

Abstract: A photovoltaic module includes a substrate, a plurality of cell sets, a first collecting electrode and a second collecting electrode. The cell sets are disposed on the substrate. Each of the cell sets includes a plurality of cell units, a bottom connecting electrode and an upper connecting electrode. The plurality of cell units are electrically connected to each other in series. The cell units are electrically connected between the bottom connecting electrode and the upper connecting electrode. The first collecting electrode is disposed on the substrate and is electrically connected to the bottom connecting electrode of every cell set. The second collecting electrode is disposed on the substrate and is electrically connected to the upper connecting electrode of every cell set. The second collecting electrode and the cell sets are substantially made of the same layer.

Abstract translation: 光伏模块包括基板，多个电池组，第一集电电极和第二集电极。 电池组设置在基板上。 每个单元组包括多个单元单元，底部连接电极和上部连接电极。 多个电池单元彼此串联电连接。 电池单元电连接在底部连接电极和上连接电极之间。 第一收集电极设置在基板上，并且电连接到每个电池组的底部连接电极。 第二集电电极设置在基板上并与每个电池组的上连接电极电连接。 第二收集电极和电池组基本上由相同的层制成。

公开(公告)号：US08259087B2

公开(公告)日：2012-09-04

申请号：US12755422

申请日：2010-04-07

Applicant: Ke-Horng Chen ,  Chi-Lin Chen ,  Yi-Chun Chen ,  Chih-Chung Chen ,  Chia-Lin Liu ,  Huai-An Li ,  Chi-Neng Mo

Inventor： Ke-Horng Chen ,  Chi-Lin Chen ,  Yi-Chun Chen ,  Chih-Chung Chen ,  Chia-Lin Liu ,  Huai-An Li ,  Chi-Neng Mo

IPC: G06F3/045

CPC classification number: G06F3/044

Abstract: In a capacitance sensing analog circuit of a touch panel sensing circuit, by raising a magnitude of a current flowing through a sensing capacitor to form an amplified sensing capacitance, while sensing the amplified sensing capacitance with the aid of pulse width modulation signals, higher resolution of the original sensing capacitance may thus be achieved. Besides, by using a self-calibrating capacitance sensing circuit on the touch panel sensing circuit, linear errors and DC errors of an output signal of the capacitance sensing analog circuit may be filtered off, and thereby resolution of a capacitance amplifying ratio may be effectively raised so as to relieve errors within the capacitance amplifying ratio caused by noises.

Abstract translation: 在触摸面板感测电路的电容感测模拟电路中，通过提高流经感测电容器的电流的大小以形成放大的感测电容，同时借助脉冲宽度调制信号感测放大的感测电容，更高的分辨率 因此可以实现原始感测电容。 此外，通过在触摸面板感测电路上使用自校准电容感测电路，可以滤除电容感测模拟电路的输出信号的线性误差和DC误差，从而可以有效地提高电容放大比的分辨率 以减轻由噪声引起的电容放大比例中的误差。

公开(公告)号：US20110254468A1

公开(公告)日：2011-10-20

申请号：US12831231

申请日：2010-07-06

Applicant: Ke-Horng Chen ,  Chi-Lin Chen ,  Yao-Yi Yang ,  Ling Li ,  Chia-Lin Liu ,  Chi-Neng Mo

Inventor： Ke-Horng Chen ,  Chi-Lin Chen ,  Yao-Yi Yang ,  Ling Li ,  Chia-Lin Liu ,  Chi-Neng Mo

IPC: H05B37/02

CPC classification number: H05B33/0818 ,  H05B33/0815

Abstract: A voltage converter for use in a backlight module stores energy of an input voltage using an inductor and outputs a plurality of output voltages accordingly. The charging path of the inductor is controlled according to the first output voltage so that the first output voltage can be stabilized. The discharging paths from the inductor to other output voltages are controlled according to the differences between other output voltages and the first output voltage so that other output voltages can also be stabilized.

Abstract translation: 用于背光模块的电压转换器使用电感器存储输入电压的能量并相应地输出多个输出电压。 根据第一输出电压来控制电感器的充电路径，使得第一输出电压可以稳定。 根据其他输出电压和第一输出电压之间的差异，从电感器到其他输出电压的放电路径进行控制，以便其他输出电压也可以稳定。