公开(公告)号：US20070018073A1

公开(公告)日：2007-01-25

申请号：US11213186

申请日：2005-08-25

Applicant: Tzu-Hsuan Hsu ,  Dun-Nian Yaung ,  Chih-Kung Chang

Inventor： Tzu-Hsuan Hsu ,  Dun-Nian Yaung ,  Chih-Kung Chang

IPC: H01L27/00

CPC classification number: H01L27/14645 ,  H01L27/14641 ,  H04N5/37457 ,  H04N9/045

Abstract: A CMOS image sensor cell includes a first pixel area in which at least one first photodiode is disposed for generating a first sense signal in response to a photo-signal of a first color; a second pixel area neighboring the first pixel area, in which at least one second photodiode is disposed for generating a second sense signal in response to a photo-signal of a second color; and a third pixel area neighboring the first and second pixel areas, in which at least one third photodiode is disposed for generating a third sense signal in response to a photo-signal of a third color. A sense amplifier is disposed substantially within the first, second and third pixel areas for amplifying the first, second and third sense signals. The first, second and third pixel areas that substantially occupy an entire area of the image sensor cell are substantially equal in size.

Abstract translation: CMOS图像传感器单元包括第一像素区域，其中至少一个第一光电二极管被设置用于响应于第一颜色的光信号产生第一感测信号; 与第一像素区域相邻的第二像素区域，其中设置至少一个第二光电二极管以响应于第二颜色的光信号产生第二感测信号; 以及与所述第一和第二像素区域相邻的第三像素区域，其中设置至少一个第三光电二极管以响应于第三颜色的光信号产生第三感测信号。 读出放大器基本上设置在第一，第二和第三像素区域内，用于放大第一，第二和第三感测信号。 基本上占据图像传感器单元的整个区域的第一，第二和第三像素区域的尺寸基本相等。

公开(公告)号：US07085168B2

公开(公告)日：2006-08-01

申请号：US11026799

申请日：2004-12-30

Applicant: Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

Inventor： Ming-Hsiu Lee ,  Chao-I Wu ,  Tzu-Hsuan Hsu

IPC: G11C16/34

CPC classification number: G11C11/5671 ,  G11C16/0475 ,  G11C16/12 ,  G11C16/3459 ,  G11C16/3481

Abstract: A method for programming one or more memory cells is disclosed. The one or more memory cells need to be two sides operated. After verifying both sides of each memory cell to identify the sides of the memory cells to be programmed, a programming voltage pulse is given to the first sides of the memory cells identified to be programmed. Another verification process is performed for both sides of each memory cell to identify the sides of the memory cells to be programmed. Next, a programming voltage pulse is given to the second sides of the memory cells identified to be programmed. The verifying both sides, programming the first sides, verifying both sides, and programming the second sides will continue until the both sides of each memory cell are programmed to a target programming voltage. The target programming voltage might have multiple voltage levels.

Abstract translation: 公开了一种用于编程一个或多个存储器单元的方法。 一个或多个存储单元需要是双面操作的。 在验证每个存储器单元的两侧以识别待编程的存储器单元的侧面之后，向被识别为被编程的存储器单元的第一侧提供编程电压脉冲。 对每个存储单元的两侧执行另一个验证过程，以识别待编程的存储器单元的侧面。 接下来，将编程电压脉冲提供给被识别为被编程的存储器单元的第二侧。 验证两侧，编程第一面，验证双面，并对第二面进行编程将一直持续到每个存储单元的两侧都编程为目标编程电压。 目标编程电压可能有多个电压电平。

公开(公告)号：US06982443B2

公开(公告)日：2006-01-03

申请号：US10799986

申请日：2004-03-12

Applicant: Tzu-Hsuan Hsu ,  Shou-Gwo Wuu ,  Ho-Ching Chien ,  Dun-Nian Yaung

Inventor： Tzu-Hsuan Hsu ,  Shou-Gwo Wuu ,  Ho-Ching Chien ,  Dun-Nian Yaung

IPC: H01L27/148 ,  H01L29/768

CPC classification number: H01L27/14632 ,  H01L27/1462

Abstract: A plurality of apertures is formed in at least one first insulating layer disposed over a sensor formed in a semiconductor substrate. A second insulating layer is disposed over the at least one first insulating layer and the plurality of apertures in the at least one first insulating layer. The apertures form hollow regions in the at least one first insulating layer over the sensor, allowing more light or energy to pass through the at least one first insulating layer to the sensor, and increasing the sensitivity of the sensor.

公开(公告)号：US20050286312A1

公开(公告)日：2005-12-29

申请号：US10873623

申请日：2004-06-23

Applicant: Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

Inventor： Chao-I Wu ,  Ming-Hsiu Lee ,  Tzu-Hsuan Hsu

IPC: G11C16/04 ,  H01L21/8247

CPC classification number: G11C16/0475

Abstract: A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.

Abstract translation: 公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。 该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。

公开(公告)号：US20050280007A1

公开(公告)日：2005-12-22

申请号：US10868827

申请日：2004-06-17

Applicant: Tzu-Hsuan Hsu ,  Dun-Nian Yaung ,  Yean-Kuen Fang

Inventor： Tzu-Hsuan Hsu ,  Dun-Nian Yaung ,  Yean-Kuen Fang

IPC: H01L25/16 ,  H01L27/146 ,  H01L27/148 ,  H01L27/15

CPC classification number: H01L27/1462 ,  H01L25/167 ,  H01L27/14625 ,  H01L27/1463 ,  H01L27/14687 ,  H01L27/14689 ,  H01L27/15 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An image sensor device and fabrication method thereof wherein a substrate having at least one shallow trench isolation structure therein is provided. At least one photosensor and at least one light emitting element, e.g., such as MOS or LED, are formed in the substrate. The photosensor and the light emitting element are isolated by the shallow trench isolation structure. An opening is formed in the shallow trench isolation structure to expose part of the substrate. An opaque shield is formed in the opening to prevent photons from the light emitting element from striking the photosensor.

Abstract translation: 一种图像传感器装置及其制造方法，其中提供其中具有至少一个浅沟槽隔离结构的基板。 在衬底中形成至少一个光电传感器和至少一个发光元件，例如MOS或LED。 光传感器和发光元件通过浅沟槽隔离结构隔离。 在浅沟槽隔离结构中形成开口以暴露部分衬底。 在开口中形成不透明屏蔽物，以防止来自发光元件的光子撞击光传感器。

公开(公告)号：US06952038B2

公开(公告)日：2005-10-04

申请号：US10728767

申请日：2003-12-08

Applicant: Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Hsiang-Lan Lung ,  Chao-I Wu

Inventor： Tzu-Hsuan Hsu ,  Ming-Hsiu Lee ,  Hsiang-Lan Lung ,  Chao-I Wu

IPC: H01L21/336 ,  H01L27/06 ,  H01L31/113

CPC classification number: H01L27/0688

Abstract: A 3D polysilicon ROM including an isolated SiO2 layer on a silicon substrate, and an N+ polysilicon layer on the isolated SiO2 layer. The N+ polysilicon layer is further defined by a plurality of parallel, separate word lines. A first oxide layer fills the space between the word lines. A dielectric layer is deposited on the word lines and the first oxide layer. A P− polysilicon layer is deposited on the dielectric layer and further defines a plurality of parallel, separate bit lines. The bit lines overlap the word lines, from a top view, to form an approximately cross shape. The neck structure may be individually formed between the P− and N+ polysilicon layers by wet etching the dielectric layer with dilute hydrofluoric acid. A second oxide layer fills the space between the bit lines and is on the word lines and the first oxide layer.

Abstract translation: 在硅衬底上包括隔离的SiO 2层的三维多晶硅ROM和分离的SiO 2层上的N +多晶硅层。 N +多晶硅层进一步由多个平行的单独的字线限定。 第一氧化物层填充字线之间的空间。 介电层沉积在字线和第一氧化物层上。 P-多晶硅层沉积在电介质层上并进一步限定多个平行的分开的位线。 位线从顶视图与字线重叠，以形成大致十字形状。 通过用稀氢氟酸湿式蚀刻介电层，可以在P和N +多晶硅层之间分别形成颈部结构。 第二氧化物层填充位线之间的空间，并且位于字线和第一氧化物层上。

公开(公告)号：US09263272B2

公开(公告)日：2016-02-16

申请号：US13474512

申请日：2012-05-17

Applicant: Min-Feng Kao ,  Szu-Ying Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Tzu-Hsuan Hsu ,  Feng-Chi Hung

Inventor： Min-Feng Kao ,  Szu-Ying Chen ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Tzu-Hsuan Hsu ,  Feng-Chi Hung

IPC: H01L29/02 ,  H01L21/265 ,  H01L21/28 ,  H01L29/423 ,  H01L23/544 ,  H01L27/146 ,  H01L21/762 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/2652 ,  H01L21/28114 ,  H01L21/76229 ,  H01L23/544 ,  H01L27/14609 ,  H01L27/1464 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device includes a semiconductor substrate, and a Device Isolation (DI) region extending from a top surface of the semiconductor substrate into the semiconductor substrate. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the DI region. A gate electrode is disposed over the gate dielectric, wherein a notch of the gate electrode overlaps a portion of the DI region.

Abstract translation: 一种器件包括半导体衬底和从半导体衬底的顶表面延伸到半导体衬底中的器件隔离（DI）区域。 栅极电介质设置在半导体衬底的有源区上，其中栅极电介质延伸超过DI区域。 栅电极设置在栅极电介质上，其中栅电极的凹口与DI区的一部分重叠。

公开(公告)号：US08975687B2

公开(公告)日：2015-03-10

申请号：US12813906

申请日：2010-06-11

Applicant: Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Sheng-Chih Lai

Inventor： Hang-Ting Lue ,  Tzu-Hsuan Hsu ,  Sheng-Chih Lai

IPC: H01L29/76 ,  H01L29/792 ,  G11C16/04 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/792 ,  G11C16/0483 ,  H01L21/26513 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

Abstract: An integrated circuit of an array of nonvolatile memory cells has a dielectric stack layer over the substrate, and implanted regions in the substrate under the dielectric stack layer. The dielectric stack layer is continuous over a planar region, that includes locations of the dielectric stack layer that store nonvolatile data, such that these locations are accessed by word lines/bit lines.

Abstract translation: 非易失性存储单元阵列的集成电路在衬底上具有介电堆叠层，并且在介电堆叠层下方的衬底中的注入区域。 电介质堆叠层在平面区域上是连续的，其包括存储非易失性数据的电介质堆叠层的位置，使得这些位置被字线/位线访问。

公开(公告)号：US08847299B2

公开(公告)日：2014-09-30

申请号：US12017064

申请日：2008-01-21

Applicant: Tzu-Hsuan Hsu ,  Yen-Hao Shih

Inventor： Tzu-Hsuan Hsu ,  Yen-Hao Shih

IPC: H01L29/76 ,  H01L27/115 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L27/115 ,  H01L29/792

Abstract: A non-volatile memory cell comprising a substrate, a charge-trapping layer, a control gate, a first conductive state of source and drain, a lightly doped region and a second conductive state of pocket-doped region. The charge-trapping layer and the control gate are disposed over the substrate. A dielectric layer is disposed between the substrate, the charge-trapping layer and the control gate. The source and drain are disposed in the substrate on each side of the charge-trapping layer. The lightly doped region is disposed on the substrate surface between the source and the charge-trapping layer. The pocket-doped region is disposed within the substrate between the drain and the charge-trapping layer. Because there are asymmetrical configuration and different doped conductive states of implant structures, the programming speed of the memory cell is increased, the neighboring cell disturb issue is prevented, and the area occupation of the bit line selection transistor is reduced.

Abstract translation: 一种非易失性存储单元，包括衬底，电荷俘获层，控制栅极，源极和漏极的第一导电状态，轻掺杂区域和第二导电状态的袋掺杂区域。 电荷捕获层和控制栅极设置在衬底上。 电介质层设置在基板，电荷俘获层和控制栅极之间。 源极和漏极设置在电荷俘获层的每一侧上的衬底中。 轻掺杂区域设置在源极和电荷捕获层之间的衬底表面上。 掺杂阱区域设置在漏极和电荷捕获层之间的衬底内。 由于存在不对称配置和掺杂导体状态的不同，存储单元的编程速度增加，从而防止了相邻单元的干扰问题，并减少了位线选择晶体管的占用面积。

公开(公告)号：US08704277B2

公开(公告)日：2014-04-22

申请号：US11624568

申请日：2007-01-18

Applicant: Tzu-Hsuan Hsu ,  Dun-Nian Yaung

Inventor： Tzu-Hsuan Hsu ,  Dun-Nian Yaung

IPC: H01L27/14

CPC classification number: H01L27/14645 ,  H01L27/14603 ,  H01L27/14621 ,  H01L27/1464

Abstract: A backside illuminated sensor includes a semiconductor substrate having a front surface and a back surface and a plurality of pixels formed on the front surface of the semiconductor substrate. A dielectric layer is disposed above the front surface of the semiconductor substrate. The sensor further includes a plurality of array regions arranged according to the plurality of pixels. At least two of the array regions have a different radiation response characteristic from each other, such as the first array region having a greater junction depth than the second array region, or the first array region having a greater dopant concentration than the second array region.

Abstract translation: 背面照明传感器包括具有前表面和后表面的半导体衬底以及形成在半导体衬底的前表面上的多个像素。 电介质层设置在半导体衬底的前表面之上。 传感器还包括根据多个像素布置的多个阵列区域。 阵列区域中的至少两个具有彼此不同的辐射响应特性，例如具有比第二阵列区域更大的结深度的第一阵列区域，或者具有比第二阵列区域更大的掺杂剂浓度的第一阵列区域。