公开(公告)号：US20060118894A1

公开(公告)日：2006-06-08

申请号：US11329185

申请日：2006-01-11

申请人： Guy Cohen ,  Qiqing Ouyang ,  Jeremy Schaub

发明人： Guy Cohen ,  Qiqing Ouyang ,  Jeremy Schaub

IPC分类号： H01L29/82 ,  H01L27/14 ,  H01L29/84

CPC分类号： H01L31/1085 ,  H01L31/02327 ,  H01L31/035272 ,  H01L31/105

摘要： A structure (and method for forming the structure) includes a photodetector, a substrate formed under the photodetector, and a barrier layer formed over the substrate. The buried barrier layer preferably includes a single or dual p-n junction, or a bubble layer for blocking or eliminating the slow photon-generated carriers in the region where the drift field is low.

公开(公告)号：US07911024B2

公开(公告)日：2011-03-22

申请号：US12707305

申请日：2010-02-17

申请人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

发明人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

IPC分类号： H01L27/102

CPC分类号： H01L29/7317

摘要： The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

摘要翻译： 本发明提供一种没有杂质掺杂的集电极的“无集电极”绝缘体上硅（SOI）双极结型晶体管（BJT）。 相反，本发明的垂直SOI BJT在其操作时使用背栅诱发的少数载流子反转层作为固有收集器。 根据本发明，SOI衬底被偏置，使得在用作集电极的基极区域的底部形成反型层。 这种器件的优点是其类似CMOS的工艺。 因此，可以简化集成方案，并且可以显着降低制造成本。 本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。

公开(公告)号：US07834399B2

公开(公告)日：2010-11-16

申请号：US11758291

申请日：2007-06-05

申请人： Thomas S. Kanarsky ,  Qiqing Ouyang ,  Haizhou Yin

发明人： Thomas S. Kanarsky ,  Qiqing Ouyang ,  Haizhou Yin

IPC分类号： H01L29/76

CPC分类号： H01L21/823807 ,  H01L21/823412 ,  H01L21/823468 ,  H01L21/823864 ,  H01L29/7843 ,  H01L29/7847

摘要： A stress-transmitting dielectric layer is formed on the at least one PFET and the at least one NFET. A tensile stress generating film, such as a silicon nitride, is formed on the at least one NFET by blanket deposition and patterning. A compressive stress generating film, which may be a refractive metal nitride film, is formed on the at least one PFET by a blanket deposition and patterning. An encapsulating dielectric film is deposited over the compress stress generating film. The stress is transferred from both the tensile stress generating film and the compressive stress generating film into the underlying semiconductor structures. The magnitude of the transferred compressive stress from the refractory metal nitride film may be from about 5 GPa to about 20 GPa. The stress is memorized during an anneal and remains in the semiconductor devices after the stress generating films are removed.

摘要翻译： 在至少一个PFET和至少一个NFET上形成应力传导电介质层。 通过毯式沉积和图案化在至少一个NFET上形成拉伸应力产生膜，例如氮化硅。 可以通过覆盖沉积和图案化在至少一个PFET上形成可以是折射金属氮化物膜的压应力产生膜。 在压缩应力产生膜上沉积密封电介质膜。 应力从拉伸应力产生膜和压缩应力产生膜转移到下面的半导体结构中。 来自难熔金属氮化物膜的转移的压缩应力的大小可以为约5GPa至约20GPa。 应力在退火期间被记忆，并且在除去应力产生膜之后保留在半导体器件中。

公开(公告)号：US07808081B2

公开(公告)日：2010-10-05

申请号：US11619511

申请日：2007-01-03

申请人： Andres Bryant ,  Qiqing Ouyang ,  Kern Rim

发明人： Andres Bryant ,  Qiqing Ouyang ,  Kern Rim

IPC分类号： H01L29/06

CPC分类号： H01L21/823807 ,  H01L21/7624 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/7849

摘要： The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a relaxed substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension.

摘要翻译： 本发明提供半导体器件及其形成方法，其中在半导体器件的器件沟道中产生单轴应变。 单轴应变可以处于张力或压缩状态，并且在平行于装置通道的方向上。 单轴应变可以通过应变诱导衬片，应变诱导孔或其组合在双轴应变衬底表面中产生。 单轴应变可以通过应变诱导孔和应变诱导衬垫的组合在松弛的衬底中产生。 本发明还提供了用应变诱导隔离区增加双轴应变的方法。 本发明还提供了CMOS器件，其中可以独立地处理CMOS衬底的器件区域以提供压缩或张力的单轴应变半导体表面。

公开(公告)号：US20100207683A1

公开(公告)日：2010-08-19

申请号：US12707305

申请日：2010-02-17

申请人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

发明人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

IPC分类号： H03K3/01 ,  H01L29/73

CPC分类号： H01L29/7317

摘要： The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

摘要翻译： 本发明提供一种没有杂质掺杂的集电极的“无集电极”绝缘体上硅（SOI）双极结型晶体管（BJT）。 相反，本发明的垂直SOI BJT在其操作时使用背栅诱发的少数载流子反转层作为固有收集器。 根据本发明，SOI衬底被偏置，使得在用作集电极的基极区域的底部形成反型层。 这种器件的优点是其类似CMOS的工艺。 因此，可以简化集成方案，并且可以显着降低制造成本。 本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。

公开(公告)号：US20090305474A1

公开(公告)日：2009-12-10

申请号：US12540862

申请日：2009-08-13

申请人： Andres Bryant ,  Qiqing Ouyang ,  Kern Rim

发明人： Andres Bryant ,  Qiqing Ouyang ,  Kern Rim

IPC分类号： H01L21/31 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/7624 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/7849

摘要： The present invention provides a semiconductor device and a method of forming thereof, in which a uniaxial strain is produced in the device channel of the semiconductor device. The uniaxial strain may be in tension or in compression and is in a direction parallel to the device channel. The uniaxial strain can be produced in a biaxially strained substrate surface by strain inducing liners, strain inducing wells or a combination thereof. The uniaxial strain may be produced in a relaxed substrate by the combination of strain inducing wells and a strain inducing liner. The present invention also provides a means for increasing biaxial strain with strain inducing isolation regions. The present invention further provides CMOS devices in which the device regions of the CMOS substrate may be independently processed to provide uniaxially strained semiconducting surfaces in compression or tension.

摘要翻译： 本发明提供半导体器件及其形成方法，其中在半导体器件的器件沟道中产生单轴应变。 单轴应变可以处于张力或压缩状态，并且在平行于装置通道的方向上。 单轴应变可以通过应变诱导衬片，应变诱导孔或其组合在双轴应变衬底表面中产生。 单轴应变可以通过应变诱导孔和应变诱导衬垫的组合在松弛的衬底中产生。 本发明还提供了用应变诱导隔离区增加双轴应变的方法。 本发明还提供了CMOS器件，其中可以独立地处理CMOS衬底的器件区域以提供压缩或张力的单轴应变半导体表面。

公开(公告)号：US20090191679A1

公开(公告)日：2009-07-30

申请号：US12020916

申请日：2008-01-28

申请人： Qiqing Ouyang ,  Kathryn T. Schonenberg

发明人： Qiqing Ouyang ,  Kathryn T. Schonenberg

IPC分类号： H01L21/8236

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： A first dielectric layer is formed over a PFET gate and an NFET gate, and lithographically patterned to expose a PFET area, while covering an NFET area. Exposed PFET active area is etched and refilled with a SiGe alloy, which applies a uniaxial compressive stress to a PFET channel. A second dielectric layer is formed over the PFET gate and the NFET gate, and lithographically patterned to expose the NFET area, while covering the PFET area. Exposed NFET active area is etched and refilled with a silicon-carbon alloy, which applies a uniaxial tensile stress to an NFET channel. Dopants may be introduced into the SiGe and silicon-carbon regions by in-situ doping or by ion implantation.

摘要翻译： 在PFET栅极和NFET栅极上形成第一电介质层，并且被光刻图案化以在覆盖NFET区域的同时暴露PFET区域。 暴露的PFET有源区被蚀刻并用SiGe合金重新填充，SiGe合金向PFET通道施加单轴压应力。 第二电介质层形成在PFET栅极和NFET栅极上，并且被光刻图案化以暴露NFET区域，同时覆盖PFET区域。 暴露的NFET有源区被蚀刻并用硅 - 碳合金重新填充，硅 - 碳合金对NFET通道施加单轴拉伸应力。 可以通过原位掺杂或通过离子注入将掺杂剂引入到SiGe和硅 - 碳区域中。

公开(公告)号：US20090174002A1

公开(公告)日：2009-07-09

申请号：US11971437

申请日：2008-01-09

申请人： Qiqing Ouyang ,  Kathryn T. Schonenberg ,  John Yates, III

发明人： Qiqing Ouyang ,  Kathryn T. Schonenberg ,  John Yates, III

IPC分类号： H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/6656 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： Source and drain extension regions are selectively removed by a dopant concentration dependent etch or a doping type dependent etch, and an embedded stress-generating material such as SiGe alloy or a Si:C alloy in the source and drain extension regions is grown on a semiconductor substrate. The embedded stress-generating material may be grown only in the source and drain extension regions, or in the source and drain extension regions and in deep source and drain regions. In one embodiment, an etch process that removes doped semiconductor regions of one conductivity type selective to doped semiconductor regions of another conductivity type may be employed. In another embodiment, a dopant concentration dependent etch process that removes doped semiconductor regions irrespective of the conductivity type selective to undoped semiconductor regions may be employed.

摘要翻译： 源极和漏极延伸区域通过掺杂剂浓度依赖性蚀刻或掺杂型依赖性蚀刻被选择性去除，并且在源极和漏极延伸区域中嵌入的应力产生材料如SiGe合金或Si：C合金生长在半导体 基质。 嵌入的应力产生材料可以仅在源极和漏极延伸区域中，或者在源极和漏极延伸区域以及深的源极和漏极区域中生长。 在一个实施例中，可以采用去除对另一种导电类型的掺杂半导体区域有选择性的一种导电类型的掺杂半导体区域的蚀刻工艺。 在另一个实施例中，可以采用去除掺杂半导体区域而不考虑对未掺杂的半导体区域有选择性的导电类型的掺杂浓度依赖蚀刻工艺。

公开(公告)号：US20080230869A1

公开(公告)日：2008-09-25

申请号：US12099437

申请日：2008-04-08

申请人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

发明人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

IPC分类号： H01L29/732 ,  H01L21/331

CPC分类号： H01L29/7317

摘要： The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

摘要翻译： 本发明提供一种没有杂质掺杂的集电极的“无集电极”绝缘体上硅（SOI）双极结型晶体管（BJT）。 相反，本发明的垂直SOI BJT在其操作时使用背栅诱发的少数载流子反转层作为固有收集器。 根据本发明，SOI衬底被偏置，使得在用作集电极的基极区域的底部形成反型层。 这种器件的优点是其类似CMOS的工艺。 因此，可以简化集成方案，并且可以显着降低制造成本。 本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。

公开(公告)号：US07375410B2

公开(公告)日：2008-05-20

申请号：US10787002

申请日：2004-02-25

申请人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

发明人： Herbert L. Ho ,  Mahender Kumar ,  Qiqing Ouyang ,  Paul A. Papworth ,  Christopher D. Sheraw ,  Michael D. Steigerwalt

IPC分类号： H01L27/102

CPC分类号： H01L29/7317

摘要： The present invention provides a “collector-less” silicon-on-insulator (SOI) bipolar junction transistor (BJT) that has no impurity-doped collector. Instead, the inventive vertical SOI BJT uses a back gate-induced, minority carrier inversion layer as the intrinsic collector when it operates. In accordance with the present invention, the SOI substrate is biased such that an inversion layer is formed at the bottom of the base region serving as the collector. The advantage of such a device is its CMOS-like process. Therefore, the integration scheme can be simplified and the manufacturing cost can be significantly reduced. The present invention also provides a method of fabricating BJTs on selected areas of a very thin BOX using a conventional SOI starting wafer with a thick BOX. The reduced BOX thickness underneath the bipolar devices allows for a significantly reduced substrate bias compatible with the CMOS to be applied while maintaining the advantages of a thick BOX underneath the CMOS.

摘要翻译： 本发明提供一种没有杂质掺杂的集电极的“无集电极”绝缘体上硅（SOI）双极结型晶体管（BJT）。 相反，本发明的垂直SOI BJT在其操作时使用背栅诱发的少数载流子反转层作为固有收集器。 根据本发明，SOI衬底被偏置，使得在用作集电极的基极区域的底部形成反型层。 这种器件的优点是其类似CMOS的工艺。 因此，可以简化集成方案，并且可以显着降低制造成本。 本发明还提供了使用具有厚BOX的常规SOI起始晶片在非常薄的BOX的选定区域上制造BJT的方法。 双极器件下面的BOX厚度减小，可以显着降低与CMOS相容的衬底偏置，同时保持CMOS下方的厚BOX的优点。