SYSTEMS AND METHODS FOR ASSIGNING CONTROLLED NODES TO CHANNEL INTERFACES OF A CONTROLLER

    公开(公告)号:US20170142607A1

    公开(公告)日:2017-05-18

    申请号:US15348845

    申请日:2016-11-10

    CPC classification number: H04W24/10 H04W24/02 H04W48/16 H04W92/22

    Abstract: Controller provides signals to controlled nodes and includes first channel interface coupled to first controlled node and second channel interface coupled to second controlled node. Controller discovers which channel interface is coupled to which controlled node by communicating first measurement request signal from first channel interface toward first controlled node; communicating second measurement request signal from second channel interface toward second controlled node; communicating power level request signal from a channel interface to first/second controlled nodes; receiving set of power levels from both first/second controlled nodes in response to power level request signal; determining that first controlled node is more strongly signal-coupled with first channel interface than second controlled node when first power level received from first controlled node is higher; and determine that second controlled node is more strongly signal-coupled with first channel interface than first controlled node when first power level received from second controlled node is higher.

    TIMESLOT MAPPING AND/OR AGGREGATION ELEMENT FOR DIGITAL RADIO FREQUENCY TRANSPORT ARCHITECTURE
    42.
    发明申请
    TIMESLOT MAPPING AND/OR AGGREGATION ELEMENT FOR DIGITAL RADIO FREQUENCY TRANSPORT ARCHITECTURE 审中-公开
    数字无线电频率传输架构的时间映射和/或累积要素

    公开(公告)号:US20160373232A1

    公开(公告)日:2016-12-22

    申请号:US15256216

    申请日:2016-09-02

    CPC classification number: H04L5/0085 H04J3/04 H04J3/16 H04W72/12

    Abstract: A serial link interface unit includes serialized data stream interfaces configured to receive a serialized data stream having a data rate and set of timeslots; an aggregate serialized data stream interface configured to communicate an aggregate serialized data stream having aggregate data rate and plurality of aggregate timeslot sets each coming sequentially in time, wherein a second aggregate timeslot set comes after a first aggregate timeslot set; and wherein the serial link interface unit interleaves data from the different serialized data streams received at the plurality of first interfaces by mapping data from a first timeslot from each different serialized data stream to the first aggregate timeslot set in the aggregate serialized data stream and mapping data from a second timeslot from each different serialized data stream to the second aggregate timeslot set in the aggregate serialized data stream.

    Abstract translation: 串行链路接口单元包括被配置为接收具有数据速率和时隙集合的串行数据流的串行数据流接口; 聚合序列化数据流接口,被配置为传送具有聚合数据速率和多个聚合时隙集合的聚合序列化数据流,每个聚合时隙集合在时间上顺序地进行,其中第二聚合时隙集合在第一聚合时隙集合之后; 并且其中所述串行链路接口单元通过将来自每个不同序列化数据流的第一时隙的数据映射到所述聚合序列化数据流中设置的所述第一聚合时隙并映射数据,从而在所述多个第一接口处接收的不同序列化数据流中的数据进行交织 从第二时隙从每个不同的序列化数据流到在聚合序列化数据流中设置的第二聚合时隙。

    Systems and methods for improved digital RF transport in distributed antenna systems

    公开(公告)号:USRE48157E1

    公开(公告)日:2020-08-11

    申请号:US15423757

    申请日:2017-02-03

    Abstract: Systems and methods for improved digital RF transport in a DAS are provided. In one embodiment, a transceiver comprises: a receive path circuit including an RF reception interface coupled to an ADC, the ADC receiving a down-converted analog RF spectrum from the RF reception interface and producing a digitized RF spectrum at an input sampling rate; a logic device receiving the digitized RF spectrum and producing a first set of baseband data samples at a first sampling rate, corresponding to a first spectral region of the analog RF spectrum and a second set of baseband data samples at a second sampling rate, corresponding to a second spectral region of the analog RF spectrum. The logic device maps the first set and second sets of baseband data samples to a respective first set and second set of timeslots of a serial data stream transport frame.

    SYSTEMS AND METHODS FOR DELAY MANAGEMENT IN DISTRIBUTED ANTENNA SYSTEM WITH DIRECT DIGITAL INTERFACE TO BASE STATION

    公开(公告)号:US20180287724A1

    公开(公告)日:2018-10-04

    申请号:US15997448

    申请日:2018-06-04

    CPC classification number: H04B17/364 H04W24/06 H04W88/085

    Abstract: A waveform generator includes circuitry configured to: generate a digital representation of a pulse and apply the digital representation of the pulse to a digital interface of a radio system configured to propagate the pulse and convert the digital representation of the pulse to a radio frequency signal transmitted at the antenna; and mark the digital representation of the pulse with respect to a frame of digital data with a marker. Measurement of when the pulse occurs in the radio frequency signal based on the marker occurs by a spectrum analyzer. Determination occurs of a downlink propagation delay for the radio system between application of the digital representation of the pulse at the digital interface and transmission of the radio frequency signal at the antenna.

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