公开(公告)号：US07139212B2

公开(公告)日：2006-11-21

申请号：US11152033

申请日：2005-06-14

Applicant: Cyrille Dray ,  Sébastien Barasinski ,  Jean Lasseuguette ,  Christophe Frey ,  Richard Fournel

Inventor： Cyrille Dray ,  Sébastien Barasinski ,  Jean Lasseuguette ,  Christophe Frey ,  Richard Fournel

IPC: G11C8/00

CPC classification number: G11C11/16

Abstract: A memory device includes at least one segmented writing line formed by at least one writing segment. A programming circuit is controlled by a line address circuit in a writing mode of the memory device to program at least one memory cell coupled to the segmented writing line. A reading bit line is connected to a reading circuit for reading the contents of the cell in a reading mode of the memory device. The reading bit line cooperates in writing mode with the line address circuit to control the programming circuit of the segmented writing line.

Abstract translation: 存储器件包括由至少一个写入段形成的至少一个分段写入线。 编程电路由存储器件的写入模式中的行地址电路控制，以对耦合到分段写入线的至少一个存储单元进行编程。 读取位线连接到用于在存储器件的读取模式下读取单元的内容的读取电路。 读取位线以写入模式与线路地址电路协作，以控制分段写入线的编程电路。

公开(公告)号：US20050281080A1

公开(公告)日：2005-12-22

申请号：US11159858

申请日：2005-06-23

Applicant: Cyrille Dray ,  Christophe Frey ,  Jean Lasseuguette ,  Sebastien Barasinski ,  Richard Fournel

Inventor： Cyrille Dray ,  Christophe Frey ,  Jean Lasseuguette ,  Sebastien Barasinski ,  Richard Fournel

IPC: G11C7/18 ,  G11C8/10 ,  G11C11/16 ,  G11C11/14

CPC classification number: G11C7/18 ,  G11C7/12 ,  G11C11/15 ,  G11C11/16

Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row. A second write signal is applied to one bit line to actuate the second selection circuit/transistor for the column corresponding to that one bit line and cause a write current to flow through the second source-drain path of the actuated second selection circuit/transistor and the corresponding write bit line to write data into at least one memory element in that column.

Abstract translation: 随机存取存储器阵列包括排列成行和列的随机存取存储器元件。 每行的元素具有字线和写数字线，并且每列的元素具有位线和写位线。 用于每行的第一选择电路/晶体管具有耦合在写入数字线中的第一源极 - 漏极通路和耦合到字线的栅极端子。 用于每列的第二选择电路/晶体管具有在写位线中耦合的第二源 - 漏路径和耦合到位线的栅极端。 第一写入信号被施加到一个字线以激活对应于该一条字线的行的第一选择电路/晶体管，并且使得写入电流流过被激活的第一选择电路/晶体管的第一源极 - 漏极路径，并且 相应的写数字行将数据写入该行中的某些存储器元素。 第二写入信号被施加到一个位线以启动与该一个位线相对应的列的第二选择电路/晶体管，并且使得写入电流流过被致动的第二选择电路/晶体管的第二源极 - 漏极通路，并且 相应的写位线将数据写入该列中的至少一个存储器元件。

公开(公告)号：US20050077924A1

公开(公告)日：2005-04-14

申请号：US10929359

申请日：2004-08-27

Applicant: Cyrille Dray

Inventor： Cyrille Dray

IPC: G11C16/12 ,  H03F3/45

CPC classification number: G11C16/12

Abstract: A switch arrangement for switching a node between three supply voltages based on two control signals. The switch arrangement includes three circuits for connecting an output node with one of three nodes, each of which is set to a different voltage. The switch arrangement is controlled by six control signals that establish mutually exclusive switching modes and avoid combinational currents. The switch arrangement is also designed to allow the use of MOS transistors having a low nominal voltage, with a value that is lower than the highest voltage to be switched. The switch arrangement is particularly adapted to supply power to non-volatile memory cells.

Abstract translation: 一种用于基于两个控制信号在三个电源电压之间切换节点的开关装置。 开关装置包括用于将输出节点与三个节点之一连接的三个电路，每个节点被设置为不同的电压。 开关布置由六个控制信号控制，这些控制信号建立互斥开关模式并避免组合电流。 开关装置还被设计为允许使用具有低额定电压的MOS晶体管，其值低于要切换的最高电压。 开关装置特别适于向非易失性存储单元供电。

公开(公告)号：US06850112B2

公开(公告)日：2005-02-01

申请号：US10470134

申请日：2002-01-23

Applicant: Cyrille Dray

Inventor： Cyrille Dray

IPC: G05F1/46 ,  G05F3/24 ,  G05F1/10

CPC classification number: G05F3/247 ,  G05F1/465

Abstract: Control device for a generation circuit (REF) for reference voltages (VPOL1, VPOL2), includes a first P type MOS transistor (M12), connected between a node (N) to which a high voltage signal (EHV) is applied and a first intermediate node (A), a second P type MOS transistor (M13) connected between the first intermediate node (A) and a second intermediate node (B), and a third P type MOS transistor (M14) connected between the second node and the ground and with its grid connected to its drain, to supply a reference voltage (VPOL1, VPOL2) on one of the first and second intermediate nodes (A, B). The control device includes a controlling mechanism for controlling the reference transistors, either in a first or second operating mode.

Abstract translation: 用于参考电压（VPOL1，VPOL2）的发生电路（REF）的控制装置包括连接在施加了高电压信号（EHV）的节点（N）和第一P型MOS晶体管（M12）之间的第一P型MOS晶体管 中间节点（A），连接在第一中间节点（A）和第二中间节点（B）之间的第二P型MOS晶体管（M13），以及第三P型MOS晶体管（M14），连接在第二节点 接地并且其电网连接到其漏极，以在第一和第二中间节点（A，B）之一上提供参考电压（VPOL1，VPOL2）。 控制装置包括用于在第一或第二操作模式中控制参考晶体管的控制机构。

公开(公告)号：US06639270B2

公开(公告)日：2003-10-28

申请号：US09921280

申请日：2001-08-02

Applicant: Cyrille Dray

Inventor： Cyrille Dray

IPC: H01L29788

CPC classification number: H01L29/42324 ,  H01L29/7886

Abstract: A non-volatile memory cell includes a MOS transistor having a ring arrangement and comprising a floating gate, a center electrode at a center of the ring arrangement and surrounding the floating gate, and at least one peripheral electrode along a periphery of the ring arrangement.