公开(公告)号：US20100277983A1

公开(公告)日：2010-11-04

申请号：US12835423

申请日：2010-07-13

申请人： Nima Mokhlesi ,  Dana Lee ,  Anubhav Khandelwal

发明人： Nima Mokhlesi ,  Dana Lee ,  Anubhav Khandelwal

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/107 ,  G11C16/3404 ,  G11C16/344 ,  G11C2211/5621

摘要： Techniques are disclosed herein for erasing non-volatile memory cells. A subset of the memory cells are pre-conditioned prior to erase. The pre-conditioning alters the threshold voltage of the memory cells in a way that may help make later calculations more accurate. As an example, memory cells along a single word line might be pre-conditioned. After the pre-conditioning, the memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.

摘要翻译： 本文公开了用于擦除非易失性存储器单元的技术。 存储器单元的子集在擦除之前被预处理。 预调节以可能有助于使后续计算更准确的方式改变存储器单元的阈值电压。 作为示例，沿着单个字线的存储器单元可以被预处理。 在预处理之后，使用试写擦除脉冲擦除存储单元。 基于试用擦除脉冲的大小和在试验擦除之后关于阈值电压分布收集的数据来确定用于第二脉冲的适当幅度。 第二个擦除脉冲用于擦除存储单元。 确定第二擦除脉冲的适当幅度可最大限度地减少或消除过度擦除。

公开(公告)号：US07907449B2

公开(公告)日：2011-03-15

申请号：US12421098

申请日：2009-04-09

申请人： Dana Lee ,  Nima Mokhlesi ,  Anubhav Khandelwal

发明人： Dana Lee ,  Nima Mokhlesi ,  Anubhav Khandelwal

IPC分类号： G11C16/06

CPC分类号： G11C16/16 ,  G11C11/5635

摘要： Techniques are disclosed herein for erasing non-volatile memory cells. The memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. In one implementation, the threshold voltages of the memory cells are not verified after the second erase. Soft programming after the second erase may be performed. The magnitude of the soft programming pulse may be determined based on the trial erase pulse. In one implementation, the memory cells'threshold voltages are not verified after the soft programming. Limiting the number of erase pulses and soft programming pulses saves time and power. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.

摘要翻译： 本文公开了用于擦除非易失性存储器单元的技术。 使用试验擦除脉冲擦除存储单元。 基于试用擦除脉冲的大小和在试验擦除之后关于阈值电压分布收集的数据来确定用于第二脉冲的适当幅度。 第二个擦除脉冲用于擦除存储单元。 在一个实现中，在第二擦除之后，不会验证存储器单元的阈值电压。 可以执行第二次擦除之后的软编程。 可以基于试用擦除脉冲来确定软编程脉冲的幅度。 在一个实现中，在软编程之后，不会验证存储单元的阈值电压。 限制擦除脉冲数和软编程脉冲可节省时间和功率。 确定第二擦除脉冲的适当幅度可最大限度地减少或消除过度擦除。

公开(公告)号：US08264890B2

公开(公告)日：2012-09-11

申请号：US12835423

申请日：2010-07-13

申请人： Nima Mokhlesi ,  Dana Lee ,  Anubhav Khandelwal

发明人： Nima Mokhlesi ,  Dana Lee ,  Anubhav Khandelwal

IPC分类号： G11C16/04

CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/107 ,  G11C16/3404 ,  G11C16/344 ,  G11C2211/5621

摘要： Techniques are disclosed herein for erasing non-volatile memory cells. A subset of the memory cells are pre-conditioned prior to erase. The pre-conditioning alters the threshold voltage of the memory cells in a way that may help make later calculations more accurate. As an example, memory cells along a single word line might be pre-conditioned. After the pre-conditioning, the memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.

摘要翻译： 本文公开了用于擦除非易失性存储器单元的技术。 存储器单元的子集在擦除之前被预处理。 预调节以可能有助于使后续计算更准确的方式改变存储器单元的阈值电压。 作为示例，沿着单个字线的存储器单元可以被预处理。 在预处理之后，使用试写擦除脉冲擦除存储单元。 基于试用擦除脉冲的大小和在试验擦除之后关于阈值电压分布收集的数据来确定用于第二脉冲的适当幅度。 第二个擦除脉冲用于擦除存储单元。 确定第二擦除脉冲的适当幅度可最大限度地减少或消除过度擦除。

公开(公告)号：US20100259987A1

公开(公告)日：2010-10-14

申请号：US12421098

申请日：2009-04-09

申请人： Dana Lee ,  Nima Mokhlesi ,  Anubhav Khandelwal

发明人： Dana Lee ,  Nima Mokhlesi ,  Anubhav Khandelwal

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/16 ,  G11C11/5635

摘要： Techniques are disclosed herein for erasing non-volatile memory cells. The memory cells are erased using a trial erase pulse. A suitable magnitude for a second pulse is determined based on the magnitude of the trial erase pulse and data collected about the threshold voltage distribution after the trial erase. The second erase pulse is used to erase the memory cells. In one implementation, the threshold voltages of the memory cells are not verified after the second erase. Soft programming after the second erase may be performed. The magnitude of the soft programming pulse may be determined based on the trial erase pulse. In one implementation, the memory cells' threshold voltages are not verified after the soft programming. Limiting the number of erase pulses and soft programming pulses saves time and power. Determining an appropriate magnitude for the second erase pulse minimizes or eliminates over-erasing.

摘要翻译： 本文公开了用于擦除非易失性存储器单元的技术。 使用试验擦除脉冲擦除存储单元。 基于试用擦除脉冲的大小和在试验擦除之后关于阈值电压分布收集的数据来确定用于第二脉冲的适当幅度。 第二个擦除脉冲用于擦除存储单元。 在一个实现中，在第二擦除之后，不会验证存储器单元的阈值电压。 可以执行第二次擦除之后的软编程。 可以基于试用擦除脉冲来确定软编程脉冲的幅度。 在一个实现中，在软编程之后，不会验证存储单元的阈值电压。 限制擦除脉冲数和软编程脉冲可节省时间和功率。 确定第二擦除脉冲的适当幅度可最大限度地减少或消除过度擦除。

公开(公告)号：US08468424B2

公开(公告)日：2013-06-18

申请号：US13024676

申请日：2011-02-10

申请人： Nima Mokhlesi ,  Henry Chin ,  Dengtao Zhao

发明人： Nima Mokhlesi ,  Henry Chin ,  Dengtao Zhao

IPC分类号： H03M13/00 ,  G11C29/00

CPC分类号： G06F12/00 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/28 ,  G11C29/00 ,  G11C29/02 ,  G11C29/028 ,  H03M13/11 ,  H03M13/37

摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding and multiple read operations to achieve greater reliability. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding read data of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. If convergence does not occur, e.g., within a set time period, the state of the non-volatile storage element is sensed again, current values of the reliability metrics in the decoder are adjusted, and the decoding again attempts to converge.

摘要翻译： 使用迭代概率解码和多次读取操作来解码存储在非易失性存储器中的数据，以实现更高的可靠性。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中，初始可靠性度量（诸如对数似然比）被用于解码一组非易失性存储元件的读取数据。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 如果没有发生收敛，例如在设定的时间周期内，再次感测到非易失性存储元件的状态，则调整解码器中的可靠性度量的当前值，并且解码再次尝试收敛。

公开(公告)号：US08368137B2

公开(公告)日：2013-02-05

申请号：US11768468

申请日：2007-06-26

申请人： Nima Mokhlesi ,  Jun Wan

发明人： Nima Mokhlesi ,  Jun Wan

IPC分类号： H01L29/788

CPC分类号： G11C5/063 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/18 ,  G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4ƒpitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer.

摘要翻译： 公开了用于在非易失性存储系统中减少位线到位线电容的结构和技术。 位线在两个分离的金属层中的每一个中以4fpitch形成，并且布置成在每个层之间交替。 在替代实施例中，在每个金属层上的每个位线之间形成屏蔽。

公开(公告)号：US08125832B2

公开(公告)日：2012-02-28

申请号：US12482696

申请日：2009-06-11

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C11/34

CPC分类号： G11C8/10 ,  G11C5/147 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3418 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

摘要： Multiple programming processes are performed for a plurality of non-volatile storage elements. Each of the programming process operates to program at least a subset of said non-volatile storage elements to a set of target conditions using program pulses. In one embodiment, a first programming pass includes soft programming and additional programming passes include the programming of data. In another embodiment, all of the programming process includes programming data. For at least a subset of said programming processes, a program pulse associated with achieving a particular result for a respective programming process is identified. The identified program pulse is used to adjust programming for a subsequent programming process.

摘要翻译： 对多个非易失性存储元件执行多个编程处理。 每个编程处理操作以使用程序脉冲将所述非易失性存储元件的至少一个子集编程到一组目标条件。 在一个实施例中，第一编程遍包括软编程，并且附加编程遍包括数据的编程。 在另一个实施例中，所有编程处理包括编程数据。 对于所述编程处理的至少一个子集，识别与实现相应编程处理的特定结果相关联的编程脉冲。 识别的编程脉冲用于调整随后编程过程的编程。

公开(公告)号：US08098526B2

公开(公告)日：2012-01-17

申请号：US12710984

申请日：2010-02-23

申请人： Nima Mokhlesi

发明人： Nima Mokhlesi

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C8/10 ,  G11C11/5642 ,  G11C16/3418

摘要： Shifts in the apparent charge stored by a charge storage region such as a floating gate in a non-volatile memory cell can occur because of electrical field coupling based on charge stored in adjacent (or other) charge storage regions. Although not exclusively, the effects are most pronounced in situations where adjacent memory cells are programmed after a selected memory cell. To account for the shift in apparent charge, one or more compensations are applied when reading storage elements of a selected word line based on the charge stored by storage elements of other word lines. Efficient compensation techniques are provided by reverse reading blocks (or portions thereof) of memory cells. By reading in the opposite direction of programming, the information needed to apply (or select the results of) an appropriate compensation when reading a selected cell is determined during the actual read operation for the adjacent word line rather than dedicating a read operation to determine the information.

摘要翻译： 由于存储在相邻（或其他）电荷存储区域中的电荷的电场耦合，可能会发生由非易失性存储单元中的诸如浮动栅极之类的电荷存储区域存储的表观电荷的变化。 尽管不是排他地，但是在选择的存储单元之后对相邻存储单元进行编程的情况下，效果最明显。 为了考虑视在电荷的偏移，基于由其他字线的存储元件存储的电荷来读取所选字线的存储元件时，应用一个或多个补偿。 高效补偿技术由存储单元的反向读取块（或其部分）提供。 通过以相反的编程方向读取，在读取所选单元格期间应用（或选择结果）所需的信息在相邻字线的实际读取操作期间被确定，而不是专用于读取操作来确定 信息。

公开(公告)号：US20110252283A1

公开(公告)日：2011-10-13

申请号：US13164401

申请日：2011-06-20

申请人： Nima Mokhlesi ,  Henry Chin ,  Dengtao Zhao

发明人： Nima Mokhlesi ,  Henry Chin ,  Dengtao Zhao

IPC分类号： G06F11/25

CPC分类号： G06F11/1068 ,  G11C2029/0411

摘要： Data stored in non-volatile storage is decoded using iterative probabilistic decoding. An error correcting code such as a low density parity check code may be used. In one approach, initial reliability metrics, such as logarithmic likelihood ratios, are used in decoding sensed states of a set of non-volatile storage element. The decoding attempts to converge by adjusting the reliability metrics for bits in code words which represent the sensed state. Soft data bits are read from the memory if the decoding fails to converge. Initial reliability metric values are provided after receiving the hard read results and at each phase of the soft bit operation(s). In one embodiment, a second soft bit is read from the memory using multiple subsets of soft bit compare levels. While reading at the second subset of compare levels, decoding can be performed based on the first subset data.

摘要翻译： 使用迭代概率解码对存储在非易失性存储器中的数据进行解码。 可以使用诸如低密度奇偶校验码的纠错码。 在一种方法中，初始可靠性度量（诸如对数似然比）被用于解码一组非易失性存储元件的感测状态。 解码通过调整表示感测状态的码字中的比特的可靠性度量来尝试收敛。 如果解码失败，则从存储器读取软数据位。 在接收到硬读取结果之后和在软位操作的每个阶段提供初始可靠性度量值。 在一个实施例中，使用软比特比较级的多个子集从存储器读取第二软比特。 当在比较级的第二子集读取时，可以基于第一子集数据执行解码。

公开(公告)号：US20110235428A1

公开(公告)日：2011-09-29

申请号：US13151938

申请日：2011-06-02

申请人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

发明人： Nima Mokhlesi ,  Dengtao Zhao ,  Henry Chin ,  Tapan Samaddar

IPC分类号： G11C16/10

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/00 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： To program a set of non-volatile storage elements, a set of programming pulses are applied to the control gates (or other terminals) of the non-volatile storage elements. The programming pulses have pulse widths that vary as a function of simulated pulse magnitude data. The programming pulses can also have pulse magnitudes that vary based on measurements taken while testing the set of non-volatile storage elements. In one embodiment, the pulse widths are determined after simulation performed prior to fabrication of the non-volatile storage elements. In another embodiment, the pulse magnitudes are calculated after fabrication of the non-volatile storage elements.

摘要翻译： 为了对一组非易失性存储元件进行编程，将一组编程脉冲施加到非易失性存储元件的控制门（或其它终端）。 编程脉冲具有根据模拟脉冲幅度数据变化的脉冲宽度。 编程脉冲还可以具有基于在测试该组非易失性存储元件时所采取的测量而变化的脉冲幅度。 在一个实施例中，在制造非易失性存储元件之前进行仿真之后确定脉冲宽度。 在另一个实施例中，在制造非易失性存储元件之后计算脉冲幅度。